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Nano102_112 Series BSP
V3.03.002
The Board Support Package for Nano102_112 Series
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#include <Nano1X2Series.h>
Data Fields | |
union { | |
__I uint32_t RBR | |
__O uint32_t THR | |
}; | |
__IO uint32_t | CTL |
__IO uint32_t | TLCTL |
__IO uint32_t | IER |
__IO uint32_t | ISR |
__IO uint32_t | TRSR |
__IO uint32_t | FSR |
__IO uint32_t | MCSR |
__IO uint32_t | TMCTL |
__IO uint32_t | BAUD |
uint32_t | RESERVE0 [2] |
__IO uint32_t | IRCR |
__IO uint32_t | ALT_CTL |
__IO uint32_t | FUN_SEL |
__IO uint32_t | BR_COMP |
@addtogroup UART Universal Asynchronous Receiver/Transmitter Controller(UART) Memory Mapped Structure for UART Controller
Definition at line 9479 of file Nano1X2Series.h.
union { ... } |
__IO uint32_t UART_T::ALT_CTL |
Bits | Field | Descriptions |
---|---|---|
[2:0] | LIN_TX_BCNT | LIN TX Break Field Count Register |
The field contains 3-bit LIN TX break field count. | ||
Note: The break field length is LIN_TX_BCNT + 8. | ||
[5:4] | LIN_HEAD_SEL | LIN Header Selection |
00 = The LIN header includes "break field". | ||
01 = The LIN header includes "break field + sync field". | ||
10 = The LIN header includes "break field + sync field + PID field". | ||
11 = Reserved. | ||
[6] | LIN_RX_EN | LIN RX Enable |
When LIN RX mode enabled and received a break field or sync field or PID field (Select by LIN_Header_SEL), the controller will generator a interrupt to CPU (INT_LIN) | ||
0 = LIN RX mode Disabled. | ||
1 = LIN RX mode Enabled. | ||
[7] | LIN_TX_EN | LIN TX Header Trigger Enable |
0 = LIN TX Header Trigger Disabled. | ||
1 = LIN TX Header Trigger Enabled. | ||
Note1: This bit will be cleared automatically and generate a interrupt to CPU (INT_LIN). | ||
Note2: If user wants to receive transmit data, it recommended to enable LIN_RX_EN bit. | ||
[8] | BIT_ERR_EN | Bit Error Detect Enable |
0 = Bit error detection Disabled. | ||
1 = Bit error detection Enabled. | ||
Note: In LIN function mode, when bit error occurs, hardware will generate an interrupt to CPU (INT_LIN). | ||
[16] | RS485_NMM | RS-485 Normal Multi-Drop Operation Mode (RS-485 NMM Mode) |
0 = RS-485 Normal Multi-drop Operation mode (NMM) Disabled. | ||
1 = RS-485 Normal Multi-drop Operation mode (NMM) Enabled. | ||
Note: It can't be active in RS-485_AAD Operation mode. | ||
[17] | RS485_AAD | RS-485 Auto Address Detection Operation Mode (RS-485 AAD Mode) |
0 = RS-485 Auto Address Detection Operation mode (AAD) Disabled. | ||
1 = RS-485 Auto Address Detection Operation mode (AAD) Enabled. | ||
Note: It can't be active in RS-485_NMM Operation mode. | ||
[18] | RS485_AUD | RS-485 Auto Direction Mode (RS-485 AUD Mode) |
0 = RS-485 Auto Direction mode (AUD) Disabled. | ||
1 = RS-485 Auto Direction mode (AUD) Enabled. | ||
Note: It can be active in RS-485_AAD or RS-485_NMM operation mode. | ||
[19] | RS485_ADD_EN | RS-485 Address Detection Enable |
This bit is used to enable RS-485 hardware address detection mode. | ||
If hardware detects address byte, and then the controller will set UART_TRSR [RS485_ADDET_F] = "1". | ||
0 = Address detection mode Disabled. | ||
1 = Address detection mode Enabled. | ||
Note: This field is used for RS-485 any operation mode. | ||
[31:24] | ADDR_PID_MATCH | Address / PID Match Value Register |
This field contains the RS-485 address match values in RS-485 Function mode. | ||
This field contains the LIN protected identifier field n LIN Function mode, software fills ID0~ID5 (ADDR_PID_MATCH [5:0]), hardware will calculate P0 and P1. | ||
Note: This field is used for RS-485 auto address detection mode or used for LIN protected identifier field (PID). |
Definition at line 10000 of file Nano1X2Series.h.
__IO uint32_t UART_T::BAUD |
Bits | Field | Descriptions |
---|---|---|
[15:0] | BRD | Baud Rate Divider |
[31] | DIV_16_EN | Divider 16 Enable |
The BRD = Baud Rate Divider, and the baud rate equation is Baud Rate = UART_CLK/ [16 * (BRD + 1)]; | ||
0 = The equation of baud rate is UART_CLK / [ (BRD+1)]. | ||
1 = The equation of baud rate is UART_CLK / [16 * (BRD+1)]. | ||
Note: In IrDA mode, this bit must disable. |
Definition at line 9925 of file Nano1X2Series.h.
__IO uint32_t UART_T::BR_COMP |
Bits | Field | Descriptions |
---|---|---|
[8:0] | BR_COMP | Baud Rate Compensation Patten |
These 9-bits are used to define the relative bit is compensated or not. | ||
BR_COMP[7:0] is used to define the compensation of UART data[7:0] and BR_COM[8] is used to define the parity bit. | ||
[31] | BR_COMP_DEC | Baud Rate Compensation Decrease |
0 = Positive (increase one module clock) compensation for each compensated bit. | ||
1 = Negative (decrease one module clock) compensation for each compensated bit. |
Definition at line 10031 of file Nano1X2Series.h.
__IO uint32_t UART_T::CTL |
Bits | Field | Descriptions |
---|---|---|
[0] | RX_RST | RX Software Reset |
When RX_RST is set, all the bytes in the receiving FIFO and RX internal state machine are cleared. | ||
0 = No effect. | ||
1 = Reset the RX internal state machine and pointers. | ||
Note: This bit will be auto cleared and take at least 3 UART engine clock cycles. | ||
[1] | TX_RST | TX Software Reset |
When TX_RST is set, all the bytes in the transmitting FIFO and TX internal state machine are cleared. | ||
0 = No effect. | ||
1 = Reset the TX internal state machine and pointers. | ||
Note: This bit will be auto cleared and take at least 3 UART engine clock cycles. | ||
[2] | RX_DIS | Receiver Disable Register |
The receiver is disabled or not (set "1" to disable receiver) | ||
0 = Receiver Enabled. | ||
1 = Receiver Disabled. | ||
Note1: In RS-485 NMM mode, user can set this bit to receive data before detecting address byte. | ||
Note2: In RS-485 AAD mode, this bit will be setting to "1" automatically. | ||
Note3: In RS-485 AUD mode and LIN "break + sync +PID" header mode, hardware will control data automatically, so don't fill any value to this bit. | ||
[3] | TX_DIS | Transfer Disable Register |
The transceiver is disabled or not (set "1" to disable transceiver) | ||
0 = Transfer Enabled. | ||
1 = Transfer Disabled. | ||
[4] | AUTO_RTS_EN | RTSn Auto-Flow Control Enable |
0 = RTSn auto-flow control. Disabled. | ||
1 = RTSn auto-flow control Enabled. | ||
Note: When RTSn auto-flow is enabled, if the number of bytes in the RX-FIFO equals the UART_FCR [RTS_Tri_Lev], the UART will reassert RTSn signal. | ||
[5] | AUTO_CTS_EN | CTSn Auto-Flow control Enable |
0 = CTSn auto-flow control Disabled | ||
1 = CTSn auto-flow control Enabled. | ||
Note: When CTSn auto-flow is enabled, the UART will send data to external device when CTSn input assert (UART will not send data to device until CTSn is asserted). | ||
[6] | DMA_RX_EN | RX DMA Enable |
This bit can enable or disable RX PDMA service. | ||
0 = RX PDMA service function Disabled. | ||
1 = RX PDMA service function Enabled. | ||
[7] | DMA_TX_EN | TX DMA Enable |
This bit can enable or disable TX PDMA service. | ||
0 = TX PDMA service function Disabled. | ||
1 = TX PDMA service function Enabled. | ||
[8] | WAKE_CTS_EN | CTSn Wake-Up Function Enable |
0 = CTSn wake-up system function Disabled. | ||
1 = Wake-up function Enabled when the system is in power-down mode, an external CTSn change will wake-up system from power-down mode. | ||
[9] | WAKE_DATA_EN | Incoming Data Wake-Up Function Enable |
0 = Incoming data wake-up system Disabled. | ||
1 = Incoming data wake-up function Enabled when the system is in power-down mode, incoming data will wake-up system from power-down mode. | ||
Note: Hardware will clear this bit when the incoming data wake-up operation finishes and "system clock" work stable | ||
[12] | ABAUD_EN | Auto-Baud Rate Detect Enable |
0 = Auto-baud rate detect function Disabled. | ||
1 = Auto-baud rate detect function Enabled. | ||
Note: When the auto-baud rate detect operation finishes, hardware will clear this bit and the associated interrupt (INT_ABAUD) will be generated (If ABAUD_IE (UART_IER [7]) be enabled). | ||
[17] | WAKE_THRESH_EN | FIFO Threshold Reach Wake-Up Function Enable Control |
0 = Received FIFO threshold reach wake-up function Disabled. | ||
1 = Received FIFO threshold reach wake-up function Enabled when the system is in power-down mode. | ||
[18] | WAKE_RS485_AAD_EN | RS-485 Address Match Wake-Up Function Enable Control |
0 = RS-485 ADD mode address match wake-up function Disabled. | ||
1 = RS-485 AAD mode address match wake-up function Enabled when the system is in power-down mode. | ||
[26:24] | PWM_SEL | PWM Channel Select For Modulation |
Select the PWM channel to modulate with the UART transmit bus. | ||
000 = PWM channel 0 modulate with UART TX. | ||
001 = PWM channel 1 modulate with UART TX. | ||
010 = PWM channel 2 modulate with UART TX. | ||
011 = PWM channel 3 modulate with UART TX. | ||
The others, no modulation of UART with PWM |
Definition at line 9581 of file Nano1X2Series.h.
__IO uint32_t UART_T::FSR |
Bits | Field | Descriptions |
---|---|---|
[0] | RX_OVER_F | RX Overflow Error Status Flag (Read Only) |
This bit is set when RX-FIFO overflow. | ||
If the number of bytes of received data is greater than RX-FIFO (UART_RBR) size, 16 bytes of UART0/UART1, this bit will be set. | ||
0 = RX FIFO is not overflow. | ||
1 = RX FIFO is overflow. | ||
Note: This bit is read only, but it can be cleared by writing "1" to it. | ||
[1] | RX_EMPTY_F | Receiver FIFO Empty (Read Only) |
This bit initiate RX-FIFO empty or not. | ||
When the last byte of RX-FIFO has been read by CPU, hardware sets this bit high. | ||
It will be cleared when UART receives any new data. | ||
0 = RX FIFO is not empty. | ||
1 = RX FIFO is empty. | ||
[2] | RX_FULL_F | Receiver FIFO Full (Read Only) |
This bit initiates RX-FIFO full or not. | ||
This bit is set when RX_POINTER_F is equal to 16, otherwise is cleared by hardware. | ||
0 = RX FIFO is not full. | ||
1 = RX FIFO is full. | ||
[4] | PE_F | Parity Error State Status Flag (Read Only) |
This bit is set to logic "1" whenever the received character does not have a valid "parity bit", and it is reset whenever the CPU writes "1" to this bit. | ||
0 = No parity error is generated. | ||
1 = Parity error is generated. | ||
Note: This bit is read only, but it can be cleared by writing "1" to it. | ||
[5] | FE_F | Framing Error Status Flag (Read Only) |
This bit is set to logic "1" whenever the received character does not have a valid "stop bit" (that is, the stop bit following the last data bit or parity bit is detected as a logic "0"), and it is reset whenever the CPU writes "1" to this bit. | ||
0 = No framing error is generated. | ||
1 = Framing error is generated. | ||
Note: This bit is read only, but it can be cleared by writing "1" to it. | ||
[6] | BI_F | Break Status Flag (Read Only) |
This bit is set to a logic "1" whenever the received data input(RX) is held in the "spacing state" (logic "0") for longer than a full word transmission time (that is, the total time of "start bit" + data bits + parity + stop bits) and it is reset whenever the CPU writes "1" to this bit. | ||
0 = No Break interrupt is generated. | ||
1 = Break interrupt is generated. | ||
Note: This bit is read only, but it can be cleared by writing "1" to it. | ||
[8] | TX_OVER_F | TX Overflow Error Interrupt Status Flag (Read Only) |
If TX-FIFO (UART_THR) is full, an additional write to UART_THR will cause this bit to logic "1". | ||
0 = TX FIFO is not overflow. | ||
1 = TX FIFO is overflow. | ||
Note: This bit is read only, but it can be cleared by writing "1" to it. | ||
[9] | TX_EMPTY_F | Transmitter FIFO Empty (Read Only) |
This bit indicates TX-FIFO empty or not. | ||
When the last byte of TX-FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. | ||
It will be cleared when writing data into THR (TX-FIFO not empty). | ||
0 = TX FIFO is not empty. | ||
1 = TX FIFO is empty. | ||
[10] | TX_FULL_F | Transmitter FIFO Full (Read Only) |
This bit indicates TX-FIFO full or not. | ||
This bit is set when TX_POINTER_F is equal to 16, otherwise is cleared by hardware. | ||
0 = TX FIFO is not full. | ||
1 = TX FIFO is full. | ||
[11] | TE_F | Transmitter Empty Status Flag (Read Only) |
Bit is set by hardware when TX is inactive. (TX shift register does not have data) | ||
Bit is cleared automatically when TX-FIFO is transfer data to TX shift register or TX is empty but the transfer does not finish. | ||
0 = TX FIFO is not empty. | ||
1 = TX FIFO is empty. | ||
[20:16] | RX_POINTER_F | RX-FIFO Pointer (Read Only) |
This field indicates the RX-FIFO Buffer Pointer. | ||
When UART receives one byte from external device, RX_POINTER_F increases one. | ||
When one byte of RX-FIFO is read by CPU, RX_POINTER_F decreases one. | ||
[28:24] | TX_POINTER_F | TX-FIFO Pointer (Read Only) |
This field indicates the TX-FIFO Buffer Pointer. | ||
When CPU writes one byte data into UART_THR, TX_POINTER_F increases one. | ||
When one byte of TX-FIFO is transferred to Transmitter Shift Register, TX_POINTER_F decreases one. |
Definition at line 9855 of file Nano1X2Series.h.
__IO uint32_t UART_T::FUN_SEL |
Bits | Field | Descriptions |
---|---|---|
[1:0] | FUN_SEL | Function Select Enable |
00 = UART function mode. | ||
01 = LIN function mode. | ||
10 = IrDA Function. | ||
11 = RS-485 Function. |
Definition at line 10015 of file Nano1X2Series.h.
__IO uint32_t UART_T::IER |
Bits | Field | Descriptions |
---|---|---|
[0] | RDA_IE | Receive Data Available Interrupt Enable |
0 = INT_RDA Masked off. | ||
1 = INT_RDA Enabled. | ||
[1] | THRE_IE | Transmit Holding Register Empty Interrupt Enable |
0 = INT_THRE Masked off. | ||
1 = INT_THRE Enabled. | ||
[2] | RLS_IE | Receive Line Status Interrupt Enable |
0 = INT_RLS Masked off. | ||
1 = INT_RLS Enabled. | ||
[3] | MODEM_IE | Modem Status Interrupt Enable |
0 = INT_MOS Masked off. | ||
1 = INT_MOS Enabled. | ||
[4] | RTO_IE | RX Time-Out Interrupt Enable |
0 = INT_TOUT Masked off. | ||
1 = INT_TOUT Enabled. | ||
[5] | BUF_ERR_IE | Buffer Error Interrupt Enable |
0 = INT_BUT_ERR Masked off. | ||
1 = INT_BUF_ERR Enabled. | ||
[6] | WAKE_IE | Wake-Up Interrupt Enable |
0 = INT_WAKE Masked off. | ||
1 = INT_WAKE Enabled. | ||
[7] | ABAUD_IE | Auto-Baud Rate Interrupt Enable |
0 = INT_ABAUD Masked off. | ||
1 = INT_ABAUD Enabled. | ||
[8] | LIN_IE | LIN Interrupt Enable |
0 = INT_LIN Masked off. | ||
1 = INT_LIN Enabled. |
Definition at line 9666 of file Nano1X2Series.h.
__IO uint32_t UART_T::IRCR |
Bits | Field | Descriptions |
---|---|---|
[1] | TX_SELECT | TX_SELECT |
0 = IrDA receiver Enabled. | ||
1 = IrDA transmitter Enabled. | ||
Note: In IrDA mode, the DIV_16_EN (UART_BAUD[31]) register must be set (the baud equation must be Clock / 16 * (BRD) | ||
[5] | INV_TX | INV_TX |
0 = No inversion. | ||
1 = Inverse TX output signal. | ||
[6] | INV_RX | INV_RX |
0 = No inversion. | ||
1 = Inverse RX input signal. |
Definition at line 9947 of file Nano1X2Series.h.
__IO uint32_t UART_T::ISR |
Bits | Field | Descriptions |
---|---|---|
[0] | RDA_IS | Receive Data Available Interrupt Flag (Read Only) |
When the number of bytes in the RX-FIFO equals the RFITL then the RDA_IF will be set. | ||
If RDA_IEN (UART_IER[0]) is set then the RDA interrupt will be generated. | ||
0 = No Receive Data available interrupt is generated. | ||
1 = Receive Data available interrupt is generated. | ||
Note: This bit is read only and it will be cleared when the number of unread bytes of RX-FIFO drops below the threshold level (RFITL). | ||
[1] | THRE_IS | Transmit Holding Register Empty Interrupt Flag (Read Only) |
This bit is set when the last data of TX-FIFO is transferred to Transmitter Shift Register. | ||
If THRE_IEN (UART_IER[1]) is set that the THRE interrupt will be generated. | ||
0 = No Transmit Holding register empty interrupt is generated. | ||
1 = Transmit Holding register empty interrupt generated. | ||
Note: This bit is read only and it will be cleared when writing data into THR (TX-FIFO not empty). | ||
[2] | RLS_IS | Receive Line Interrupt Status Flag (Read Only) |
This bit is set when the RX received data has parity error (PE_F (UART_FSR[4])), framing error (FE_F (UART_FSR[5])), break error (BI_F (UART_FSR[6])) or RS-485 detect address byte (RS-485_ADDET_F (UART_TRSR[0])).If RLS_IE (UART_IER[2]) is set then the RLS interrupt will be generated. | ||
0 = No Receive Line interrupt is generated. | ||
1 = Receive Line interrupt is generated. | ||
Note1: This bit is read only, but can be cleared by it by writing "1" to BI_F (UART_FSR[6]), FE_F (UART_FSR[5]), PE_F (UART_FSR[4]) or RS-485_ADDET_F (UART_TRSR[0]). | ||
Note2: This bit is cleared when the BI_F, FE_F, PE_F and RS-485_ADDET_F are cleared. | ||
[3] | MODEM_IS | MODEM Interrupt Status Flag (Read Only) |
This bit is set when the CTSn pin has state change (DCTSF = "1"). | ||
If MODEM_IEN (UART_IER[3]) is set then the modem interrupt will be generated. | ||
0 = No MODEM interrupt is generated. | ||
1 = MODEM interrupt is generated. | ||
Note: This bit is read only, but can be cleared by it by writing "1" to DCT_F (UART_MCSR[18]). | ||
[4] | RTO_IS | RX Time-Out Interrupt Status Flag (Read Only) |
This bit is set when the RX-FIFO is not empty and no activities occur in the RX-FIFO and the time-out counter equal to TOIC. | ||
If RTO_IE (UART_IER[4]) is set then the tout interrupt will be generated. | ||
0 = No RX Time-Out interrupt is generated. | ||
1 = RX Time-Out interrupt is generated. | ||
Note: This bit is read only and user can read UART_RBR (RX is in active) to clear it. | ||
[5] | BUF_ERR_IS | Buffer Error Interrupt Status Flag (Read Only) |
This bit is set when the TX or RX-FIFO overflowed. | ||
When BUF_ERR_IS is set, the transfer maybe not correct. | ||
If BUF_ERR_IE (UART_IER[5]) is set then the buffer error interrupt will be generated. | ||
0 = No Buffer error interrupt is generated. | ||
1 = Buffer error interrupt is generated. | ||
Note1: This bit is read only, but can be cleared by it by writing "1" to TX_OVER_F (UART_FSR[8]) or RX_OVER_F (UART_FSR[0]). | ||
Note2: This bit is cleared when both the TX_OVER_F and RX_OVER_F are cleared. | ||
[6] | WAKE_IS | Wake-Up Interrupt Status Flag (Read Only) |
This bit is set in Power-down mode, the receiver received data or CTSn signal. | ||
If WAKE_IE (UART_IER[6]) is set then the wake-up interrupt will be generated. | ||
0 = No Wake-Up interrupt is generated. | ||
1 = Wake-Up interrupt is generated. | ||
Note: This bit is read only, but can be cleared by it by writing "1" to it. | ||
[7] | ABAUD_IS | Auto-Baud Rate Interrupt Status Flag (Read Only) |
This bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABAUD_IE (UART_IER[7]) is set then the auto-baud rate interrupt will be generated. | ||
0 = No Auto-Baud Rate interrupt is generated. | ||
1 = Auto-Baud Rate interrupt is generated. | ||
Note1: This bit is read only, but can be cleared by it by writing "1" to ABAUD_TOUT_F (UART_TRSR[2]) or ABAUD_F (UART_TRSR[1]). | ||
Note2: This bit is cleared when both the ABAUD_TOUT_F and ABAUD_F are cleared. | ||
[8] | LIN_IS | LIN Interrupt Status Flag (Read Only) |
This bit is set when the LIN TX header transmitted, RX header received or the SIN does not equal SOUT and if LIN_IE(UART_IER[8]) is set then the LIN interrupt will be generated. | ||
0 = No LIN interrupt is generated. | ||
1 = LIN interrupt is generated. | ||
Note1: This bit is read only, but can be cleared by it by writing "1" to BIT_ERR_F (UART_TRSR[5]), LIN_TX_F (UART_TRSR[3]) or LIN_RX_F (UART_TRSR[4]). | ||
Note2: This bit is cleared when both the BIT_ERR_F, LIN_TX_F and LIN_RX_F are cleared. |
Definition at line 9732 of file Nano1X2Series.h.
__IO uint32_t UART_T::MCSR |
Bits | Field | Descriptions |
---|---|---|
[0] | LEV_RTS | RTSn Trigger Level |
This bit can change the RTSn trigger level. | ||
0 = low level triggered. | ||
1 = high level triggered. | ||
Note: In RS-485 AUD mode and RTS Auto-flow control mode, hardware will control the output RTS pin automatically, so the table indicates the default value. | ||
Note: The default setting in UART mode is LEV_RTS = "0" and RTS_ST = "1". | ||
[1] | RTS_ST | RTSn Pin State (Read Only) |
This bit is the pin status of RTSn. | ||
0 = RTS pin input is low level voltage logic state. | ||
1 = RTS pin input is high level voltage logic state. | ||
[16] | LEV_CTS | CTSn Trigger Level |
This bit can change the CTSn trigger level. | ||
0 = Low level triggered. | ||
1 = High level triggered. | ||
[17] | CTS_ST | CTSn Pin Status (Read Only) |
This bit is the pin status of CTSn. | ||
0 = CTS pin input is low level voltage logic state. | ||
1 = CTS pin input is high level voltage logic state. | ||
[18] | DCT_F | Detect CTSn State Change Status Flag (Read Only) |
This bit is set whenever CTSn input has change state, and it will generate Modem interrupt to CPU when MODEM_IE (UART_IER[3]). | ||
0 = CTS input has not change state. | ||
1 = CTS input has change state. | ||
Note: This bit is read only, but it can be cleared by writing "1" to it. |
Definition at line 9888 of file Nano1X2Series.h.
__I uint32_t UART_T::RBR |
Bits | Field | Descriptions |
---|---|---|
[7:0] | RBR | Receiving Buffer |
By reading this register, the UART Controller will return an 8-bit data received from RX pin (LSB first). |
Definition at line 9496 of file Nano1X2Series.h.
uint32_t UART_T::RESERVE0[2] |
Definition at line 9926 of file Nano1X2Series.h.
__O uint32_t UART_T::THR |
Bits | Field | Descriptions |
---|---|---|
[7:0] | THR | Transmit Buffer |
By writing to this register, the UART sends out an 8-bit data through the TX pin (LSB first). |
Definition at line 9509 of file Nano1X2Series.h.
__IO uint32_t UART_T::TLCTL |
Bits | Field | Descriptions |
---|---|---|
[1:0] | DATA_LEN | Data Length |
00 = 5 bits. | ||
01 = 6 bits. | ||
10 = 7 bits. | ||
11 = 8 bits. | ||
[2] | NSB | Number Of STOP Bit Length |
1 = 1.5 "STOP bit" is generated in the transmitted data when 5-bit word length is selected, and 2 STOP bit" is generated when 6, 7 and 8 bits data length is selected. | ||
0 = 1 " STOP bit" is generated in the transmitted data. | ||
[3] | PBE | Parity Bit Enable |
1 = Parity bit is generated or checked between the "last data"word "it" and "stop bit" of the serial data. | ||
0 = Parity bit is not generated (transmitting data) or checked (receiving data) during transfer. | ||
[4] | EPE | Even Parity Enable |
1 = Even number of logic 1's are transmitted or check the data word and parity bits in receiving mode. | ||
0 = Odd number of logic 1's are transmitted or check the data word and parity bits in receiving mode. | ||
Note: This bit has effect only when PBE bit (parity bit enable) is set. | ||
[5] | SPE | Stick Parity Enable |
1 = When bits PBE, EPE and SPE are set, the parity bit is transmitted and checked as "0". | ||
When PBE and SPE are set and EPE is cleared, the parity bit is transmitted and checked as "1". | ||
In RS-485 mode, PBE, EPE and SPE can control bit 9. | ||
0 = Stick parity Disabled. | ||
[6] | BCB | Break Control Bit |
When this bit is set to logic "1", the serial data output (TX) is forced to the Spacing State (logic "0"). | ||
This bit acts only on TX pin and has no effect on the transmitter logic. | ||
1 = Break control Enabled. | ||
0 = Break control Disabled. | ||
[9:8] | RFITL | RX-FIFO Interrupt (INT_RDA) Trigger Level |
When the number of bytes in the receiving FIFO is equal to the RFITL then the RDA_IF will be set (if RDA_IE(IER[0]) is enabled, an interrupt will be generated) | ||
00 = RX FIFO Interrupt Trigger Level is 1 byte. | ||
01 = RX FIFO Interrupt Trigger Level is 4 bytes. | ||
10 = RX FIFO Interrupt Trigger Level is 8 bytes. | ||
11 = RX FIFO Interrupt Trigger Level is 14 bytes. | ||
Note: When operating in IrDA mode or RS-485 mode, the RFITL must be set to "0". | ||
[13:12] | RTS_TRI_LEV | RTSn Trigger Level (For Auto-Flow Control Use) |
00 = RTS Trigger Level is 1 byte. | ||
01 = RTS Trigger Level is 4 bytes. | ||
10 = RTS Trigger Level is 8 bytes. | ||
11 = RTS Trigger Level is 14 bytes. | ||
Note: This field is used for auto RTSn flow control. |
Definition at line 9629 of file Nano1X2Series.h.
__IO uint32_t UART_T::TMCTL |
Bits | Field | Descriptions |
---|---|---|
[8:0] | TOIC | Time-Out Comparator |
The time-out counter resets and starts counting whenever the RX-FIFO receives a new data word. | ||
Note1: Fill all "0" to this field indicates to disable this function. | ||
Note2: The real time-out value is TOIC + 1. | ||
Note3: The counting clock is baud rate clock. | ||
Note4: The UART data format is start bit + 8 data bits + parity bit + stop bit, although software can configure this field by any value but it is recommend to filled this field great than 0xA. | ||
[23:16] | DLY | TX Delay Time Value |
This field is use to program the transfer delay time between the last stop bit and next start bit. | ||
Note1: Fill all "0" to this field indicates to disable this function. | ||
Note2: The real delay value is DLY. | ||
Note3: The counting clock is baud rate clock. |
Definition at line 9909 of file Nano1X2Series.h.
__IO uint32_t UART_T::TRSR |
Bits | Field | Descriptions |
---|---|---|
[0] | RS485_ADDET_F | RS-485 Address Byte Detection Status Flag (Read Only) |
This bit is set to logic "1" and set RS-485_ADD_EN (UART_ALT_CTL[19]) whenever in RS-485 mode the receiver detected any address byte character (bit 9 ='1') bit". | ||
This bit is reset whenever the CPU writes "1" to this bit. | ||
0 = No RS-485 address detection interrupt is generated. | ||
1 = RS-485 address detection interrupt is generated. | ||
Note1: This field is used for RS-485 mode. | ||
Note2: This bit is read only, but can be cleared by writing "1" to it. | ||
[1] | ABAUD_F | Auto-Baud Rate Interrupt (Read Only) |
This bit is set to logic "1" when auto-baud rate detect function finished. | ||
0 = No Auto- Baud Rate interrupt is generated. | ||
1= Auto-Baud Rate interrupt is generated. | ||
Note: This bit is read only, but can be cleared by writing "1" to it. | ||
[2] | ABAUD_TOUT_F | Auto-Baud Rate Time-Out Interrupt (Read Only) |
This bit is set to logic "1" in Auto-baud Rate Detect mode and the baud rate counter is overflow. | ||
0 = No Auto-Baud Rate Time-Out interrupt is generated. | ||
1 = Auto-Baud Rate Time-Out interrupt is generated. | ||
Note: This bit is read only, but can be cleared by writing "1" to it. | ||
[3] | LIN_TX_F | LIN TX Interrupt Flag (Read Only) |
This bit is set to logic "1" when LIN transmitted header field. | ||
The header may be "break field" or "break field + sync field" or "break field + sync field + PID field", it can be choose by setting LIN_HEAD_SEL (UART_ALT_CTL[5:4]) register. | ||
0 = No LIN Tx interrupt is generated. | ||
1 = LIN Tx interrupt is generated. | ||
Note: This bit is read only, but can be cleared by writing "1" to it. | ||
[4] | LIN_RX_F | LIN RX Interrupt Flag (Read Only) |
This bit is set to logic "1" when received LIN header field. | ||
The header may be "break field" or "break field + sync field" or "break field + sync field + PID field", and it can be choose by setting LIN_HEAD_SEL (UART_ALT_CTL[5:4]) register. | ||
0 = No LIN Rx interrupt is generated. | ||
1 = LIN Rx interrupt is generated. | ||
Note: This bit is read only, but can be cleared by writing "1" to it. | ||
[5] | BIT_ERR_F | Bit Error Detect Status Flag (Read Only) |
At TX transfer state, hardware will monitoring the bus state, if the input pin (SIN) state is not equal to the output pin (SOUT) state, BIT_ERR_F will be set. | ||
When occur bit error, hardware will generate an interrupt to CPU (INT_LIN). | ||
0 = No Bit error interrupt is generated. | ||
1 = Bit error interrupt is generated. | ||
Note1: This bit is read only, but it can be cleared by writing "1" to it. | ||
Note2: This bit is only valid when enabling the bit error detection function (BIT_ERR_EN (UART_ALT_CTL[8]) = "1"). | ||
[8] | LIN_RX_SYNC_ERR_F | LIN RX SYNC Error Flag (Read Only) |
This bit is set to logic "1" when LIN received incorrect SYNC field. | ||
User can choose the header by setting LIN_HEAD_SEL (UART_ALT_CTL[5:4]) register. | ||
0 = No LIN Rx sync error is generated. | ||
1 = LIN Rx sync error is generated. | ||
Note: This bit is read only, but can be cleared by writing "1" to LIN_RX_F. |
Definition at line 9784 of file Nano1X2Series.h.