Nano102_112 Series BSP  V3.03.002
The Board Support Package for Nano102_112 Series
Data Fields
CLK_T Struct Reference

#include <Nano1X2Series.h>

Data Fields

__IO uint32_t PWRCTL
 
__IO uint32_t AHBCLK
 
__IO uint32_t APBCLK
 
__I uint32_t CLKSTATUS
 
__IO uint32_t CLKSEL0
 
__IO uint32_t CLKSEL1
 
__IO uint32_t CLKSEL2
 
__IO uint32_t CLKDIV0
 
__IO uint32_t CLKDIV1
 
__IO uint32_t PLLCTL
 
__IO uint32_t FRQDIV0
 
uint32_t RESERVE0 [1]
 
__IO uint32_t WK_INTSTS
 
__IO uint32_t APB_DIV
 
__IO uint32_t FRQDIV1
 
__IO uint32_t SP_DET
 
__I uint32_t SP_STS
 

Detailed Description

@addtogroup CLK System Clock Controller(CLK)
Memory Mapped Structure for CLK Controller

Definition at line 903 of file Nano1X2Series.h.

Field Documentation

◆ AHBCLK

__IO uint32_t CLK_T::AHBCLK

AHBCLK

Offset: 0x04 AHB Devices Clock Enable Control Register

Bits Field Descriptions
[0] GPIO_EN GPIO Controller Clock Enable Control
0 = Disabled.
1 = Enabled.
[1] DMA_EN DMA Controller Clock Enable Control
0 = Disabled.
1 = Enabled.
[2] ISP_EN Flash ISP Controller Clock Enable Control
0 = Disabled.
1 = Enabled.
[4] SRAM_EN SRAM Controller Clock Enable Control
0 = Disabled.
1 = Enabled.
[5] TICK_EN System Tick Clock Enable Control
0 = Disabled.
1 = Enabled.

Definition at line 1008 of file Nano1X2Series.h.

◆ APB_DIV

__IO uint32_t CLK_T::APB_DIV

APB_DIV

Offset: 0x34 APB Clock Divider

Bits Field Descriptions
[2:0] APBDIV APB Clock Divider
APB PCLK can be divided from HCLK.
000: PCLK = HCLK.
001: PCLK =1/2 HCLK.
010: PCLK = 1/4 HCLK.
011: PCLK = 1/8 HCLK.
100: PCLK = 1/16 HCLK.
Others: PCLK = HCLK.

Definition at line 1354 of file Nano1X2Series.h.

◆ APBCLK

__IO uint32_t CLK_T::APBCLK

APBCLK

Offset: 0x08 APB Devices Clock Enable Control Register

Bits Field Descriptions
[0] WDT_EN Watchdog Timer Clock Enable Control
This is a protected register. Please refer to open lock sequence to program it.
This bit is used to control the WDT APB clock only, The WDT engine Clock Source is from LIRC.
0 = Disabled.
1 = Enabled.
[1] RTC_EN Real-Time-Clock Clock Enable Control
This bit is used to control the RTC APB clock only, The RTC engine Clock Source is from LXT.
0 = Disabled.
1 = Enabled.
[2] TMR0_EN Timer0 Clock Enable Control
0 = Disabled.
1 = Enabled.
[3] TMR1_EN Timer1 Clock Enable Control
0 = Disabled.
1 = Enabled.
[4] TMR2_EN Timer2 Clock Enable Control
0 = Disabled.
1 = Enabled.
[5] TMR3_EN Timer3 Clock Enable Control
0 = Disabled.
1 = Enabled.
[6] FDIV0_EN Frequency Divider0 Output Clock Enable Control
0 = Disabled.
1 = Enabled.
[7] FDIV1_EN Frequency Divider1 Output Clock Enable Control
0 = Disabled.
1 = Enabled.
[8] I2C0_EN I2C0 Clock Enable Control
0 = Disabled.
1 = Enabled.
[9] I2C1_EN I2C1 Clock Enable Control
0 = Disabled.
1 = Enabled.
[11] ACMP_EN ACMP Clock Enable Control
0 = Disabled.
1 = Enabled.
[12] SPI0_EN SPI0 Clock Enable Control
0 = Disabled.
1 = Enabled.
[13] SPI1_EN SPI1 Clock Enable Control
0 = Disabled.
1 = Enabled.
[16] UART0_EN UART0 Clock Enable Control
0 = Disabled.
1 = Enabled.
[17] UART1_EN UART1 Clock Enable Control
0 = Disabled.
1 = Enabled.
[20] PWM0_CH01_EN PWM0 Channel 0 And Channel 1Clock Enable Control
0 = Disabled.
1 = Enabled.
[21] PWM0_CH23_EN PWM0 Channel 2 And Channel 3 Clock Enable Control
0 = Disabled.
1 = Enabled.
[26] LCD_EN LCD Controller Clock Enable Control
0 = Disabled.
1 = Enabled.
[28] ADC_EN Analog-Digital-Converter (ADC) Clock Enable Control
0 = Disabled.
1 = Enabled.
[30] SC0_EN SmartCard 0 Clock Enable Control
0 = Disabled.
1 = Enabled.
[31] SC1_EN SmartCard 1 Clock Enable Control
0 = Disabled.
1 = Enabled.

Definition at line 1084 of file Nano1X2Series.h.

◆ CLKDIV0

__IO uint32_t CLK_T::CLKDIV0

CLKDIV0

Offset: 0x1C Clock Divider Number Register 0

Bits Field Descriptions
[3:0] HCLK_N HCLK Clock Divide Number From HCLK Clock Source
The HCLK clock frequency = (HCLK Clock Source frequency) / (HCLK_N + 1).
[11:8] UART_N UART Clock Divide Number From UART Clock Source
The UART clock frequency = (UART Clock Source frequency ) / (UART_N + 1).
[23:16] ADC_N ADC Clock Divide Number From ADC Clock Source
The ADC clock frequency = (ADC Clock Source frequency ) / (ADC_N + 1).
[31:28] SC0_N SC 0 Clock Divide Number From SC 0 Clock Source
The SC 0 clock frequency = (SC0 Clock Source frequency ) / (SC0_N + 1).

Definition at line 1247 of file Nano1X2Series.h.

◆ CLKDIV1

__IO uint32_t CLK_T::CLKDIV1

CLKDIV1

Offset: 0x20 Clock Divider Number Register 1

Bits Field Descriptions
[3:0] SC1_N SC 1 Clock Divide Number From SC 1 Clock Source
The SC 1 clock frequency = (SC 1 Clock Source frequency ) / (SC1_N + 1).
[11:8] TMR0_N Timer0 Clock Divide Number From Timer0 Clock Source
The Timer0 clock frequency = (Timer0 Clock Source frequency ) / (TMR0_N + 1).
[15:12] TMR1_N Timer1 Clock Divide Number From Timer1 Clock Source
The Timer1 clock frequency = (Timer1 Clock Source frequency ) / (TMR1_N + 1).
[19:16] TMR2_N Timer2 Clock Divide Number From Timer2 Clock Source
The Timer2 clock frequency = (Timer2 Clock Source frequency ) / (TMR2_N + 1).
[23:20] TMR3_N Timer3 Clock Divide Number From Timer3 Clock Source
The Timer3 clock frequency = (Timer3 Clock Source frequency ) / (TMR3_N + 1).

Definition at line 1267 of file Nano1X2Series.h.

◆ CLKSEL0

__IO uint32_t CLK_T::CLKSEL0

CLKSEL0

Offset: 0x10 Clock Source Select Control Register 0

Bits Field Descriptions
[2:0] HCLK_S HCLK Clock Source Selection
This is a protected register. Please refer to open lock sequence to program it.
Note: Before Clock Source switches, the related clock sources (pre-select and new-select) must be turn on
The 3-bit default value is reloaded with the value of CFOSC (Config0[26:24]) in user configuration register in Flash controller by any reset.
Therefore the default value is either 000b or 111b.
000 = HXT
001 = LXT
010 = PLL Clock
011 = LIRC
111 = HIRC
Others = Reserved

Definition at line 1134 of file Nano1X2Series.h.

◆ CLKSEL1

__IO uint32_t CLK_T::CLKSEL1

CLKSEL1

Offset: 0x14 Clock Source Select Control Register 1

Bits Field Descriptions
[1:0] UART_S UART 0/1 Clock Source Selection (UART0 And UART1 Use The Same Clock Source Selection)
00 = HXT
01 = LXT
10 = PLL Clock
11 = HIRC
[5:4] PWM0_CH01_S PWM0 Channel 0 And Channel 1 Clock Source Selection
PWM0 channel 0 and channel 1 use the same Engine clock source, both of them with the same prescaler
00 = HXT
01 = LXT
10 = HCLK
11 = HIRC
[7:6] PWM0_CH23_S PWM0 Channel 2 And Channel 3 Clock Source Selection
PWM0 channel 2 and channel 3 use the same Engine clock source, both of them with the same prescaler
00 = HXT
01 = LXT
10 = HCLK
11 = HIRC
[10:8] TMR0_S Timer0 Clock Source Selection
000 = HXT
001 = LXT
010 = LIRC
011 = External Pin
100 = HIRC
Others = HCLK
[14:12] TMR1_S Timer1 Clock Source Selection
000 = HXT
001 = LXT
010 = LIRC
011 = External Pin
100 = HIRC
Others = HCLK
[18] LCD_S LCD Clock Source Selection
0 = Clock Source from LXT.
1 = Reserved.
[21:19] ADC_S ADC Clock Source Selection
000 = HXT
001 = LXT
010 = PLL clock
011 = HIRC
others = HCLK

Definition at line 1184 of file Nano1X2Series.h.

◆ CLKSEL2

__IO uint32_t CLK_T::CLKSEL2

CLKSEL2

Offset: 0x18 Clock Source Select Control Register 2

Bits Field Descriptions
[1:0] FRQDIV1_S Clock Divider Clock1 Source Selection
00 = HXT
01 = LXT
10 = HCLK
11 = HIRC
[3:2] FRQDIV0_S Clock Divider0 Clock Source Selection
00 = HXT
01 = LXT
10 = HCLK
11 = HIRC
[10:8] TMR2_S Timer2 Clock Source Selection
000 = HXT
001 = LXT
010 = LIRC
011 = External Pin
100 = HIRC
Others = HCLK
[14:12] TMR3_S Timer3 Clock Source Selection
000 = HXT
001 = LXT
010 = LIRC
011 = External Pin
100 = HIRC
Others = HCLK
[19:18] SC_S SC Clock Source Selection
00 = HXT
01 = PLL Clock
10 = HIRC
11 = HCLK
[20] SPI0_S SPI0 Clock Source Selection
0 = PLL.
1 = HCLK.
[21] SPI1_S SPI1 Clock Source Selection
0 = PLL.
1 = HCLK.

Definition at line 1229 of file Nano1X2Series.h.

◆ CLKSTATUS

__I uint32_t CLK_T::CLKSTATUS

CLKSTATUS

Offset: 0x0C Clock status monitor Register

Bits Field Descriptions
[0] HXT_STB HXT Clock Source Stable Flag
0 = HXT clock is not stable or not enable.
1 = HXT clock is stable.
[1] LXT_STB LXT Clock Source Stable Flag
0 = LXT clock is not stable or not enable.
1 = LXT clock is stable.
[2] PLL_STB PLL Clock Source Stable Flag
0 = PLL clock is not stable or not enable.
1 = PLL clock is stable.
[3] LIRC_STB LIRC Clock Source Stable Flag
0 = LIRC clock is not stable or not enable.
1 = LIRC clock is stable.
[4] HIRC_STB HIRC Clock Source Stable Flag
0 = HIRC clock is not stable or not enable.
1 = HIRC clock is stable.
[7] CLK_SW_FAIL Clock Switch Fail Flag
0 = Clock switch success.
1 = Clock switch fail.
This bit will be set when target switch Clock Source is not stable. This bit is write 1 clear

Definition at line 1113 of file Nano1X2Series.h.

◆ FRQDIV0

__IO uint32_t CLK_T::FRQDIV0

FRQDIV0

Offset: 0x28 Frequency Divider0 Control Register

Bits Field Descriptions
[3:0] FSEL Divider Output Frequency Selection Bits
The formula of output frequency is
FCLK0 = FRQDIV0_CLK/2^(N+1),.
Where FRQDIV0_CLK is the input clock frequency, Fout is the frequency of divider output clock and N is the 4-bit value of FSEL[3:0].
[4] FDIV_EN Frequency Divider Enable Bit
0 = Frequency Divider Disabled.
1 = Frequency Divider Enabled.
[5] DIV1 Output Frequency Divide By 1
0 = Output frequency is equal to FCLK0.
1 = Output frequency is equal to FRQDIV0_CLK.

Definition at line 1320 of file Nano1X2Series.h.

◆ FRQDIV1

__IO uint32_t CLK_T::FRQDIV1

FRQDIV1

Offset: 0x38 Frequency Divider1 Control Register

Bits Field Descriptions
[3:0] FSEL Divider Output Frequency Selection Bits
The formula of output frequency is
FCLK1 = FRQDIV1_CLK /2^(N+1),.
Where FRQDIV1_CLK is the input clock frequency, Fout is the frequency of divider output clock and N is the 4-bit value of FSEL[3:0].
[4] FDIV_EN Frequency Divider Enable Bit
0 = Frequency Divider Disabled.
1 = Frequency Divider Enabled.
[5] DIV1 Output Frequency Divide By 1
0 = Output frequency is equal to FCLK1.
1 = Output frequency is equal to FRQDIV1_CLK.

Definition at line 1374 of file Nano1X2Series.h.

◆ PLLCTL

__IO uint32_t CLK_T::PLLCTL

PLLCTL

Offset: 0x24 PLL Control Register

Bits Field Descriptions
[5:0] PLL_MLP PLL Multiple
000000: Reserved
000001: X1
000010: X2
000011: X3
000100: X4
...
010000:X16
...
100000: X32
0thers: Reserved
PLL output frequency: PLL input frequency * PLL_MLP.
PLL output frequency range: 16MHz ~ 32MHz
[11:8] PLL_SRC_N PLL Input Source Divider
The PLL input clock frequency = (PLL Clock Source frequency ) / (PLL_SRC_N + 1).
PLL input clock frequency range: 0.8MHz ~ 2MHz
[16] PD Power-Down Mode
If set the PD_EN bit "1" in PWR_CTL register, the PLL will enter Power-down mode too
0 = PLL is in normal mode.
1 = PLL is in power-down mode (default).
[17] PLL_SRC PLL Source Clock Select
0 = PLL source clock from HXT.
1 = PLL source clock from HIRC.

Definition at line 1300 of file Nano1X2Series.h.

◆ PWRCTL

__IO uint32_t CLK_T::PWRCTL

PWRCTL

Offset: 0x00 System Power-down Control Register

Bits Field Descriptions
[0] HXT_EN HXT Enable Control
This is a protected register. Please refer to open lock sequence to program it.
The bit default value is set by flash controller user configuration register config0 [26].
0 = Disabled.
1 = Enabled.
HXT is disabled by default.
[1] LXT_EN LXT Enable Control
This is a protected register. Please refer to open lock sequence to program it.
0 = Disabled.
1 = Enabled.
LXT is disabled by default.
[2] HIRC_EN HIRC Enable Control
This is a protected register. Please refer to open lock sequence to program it.
0 = Disabled.
1 = Enabled.
HIRC is enabled by default.
[3] LIRC_EN LIRC Enable Control
This is a protected register. Please refer to open lock sequence to program it.
0 = Disabled.
1 = Enabled.
LIRC is enabled by default.
[4] WK_DLY Wake-Up Delay Counter Enable Control
This is a protected register. Please refer to open lock sequence to program it.
When chip wakes up from Power-down mode, the clock control will delay 4096 clock cycles to wait HXT stable or 16 clock cycles to wait HIRC stable.
0 = Delay clock cycle Disabled.
1 = Delay clock cycle Enabled.
[5] PD_WK_IE Power-Down Mode Wake-Up Interrupt Enable Control
This is a protected register. Please refer to open lock sequence to program it.
0 = Disabled.
1 = Enabled.
PD_WK_INT will be set if both PD_WK_IS and PD_WK_IE are high.
[6] PD_EN Chip Power-Down Mode Enable Bit
This is a protected register. Please refer to open lock sequence to program it.
When CPU sets this bit, the chip power down is enabled and chip will not enter Power-down mode until CPU sleep mode is also active.
When chip wakes up from Power-down mode, this bit will be auto cleared.
When chip is in Power-down mode, the LDO, HXT and HIRC will be disabled, but LXT and LIRC are not controlled by Power-down mode.
When power down, the PLL and system clock (CPU, HCLKx and PCLKx) are also disabled no matter the Clock Source selection.
Peripheral clocks are not controlled by this bit, if peripheral Clock Source is from LXT or LIRC.
In Power-down mode, flash macro power is ON.
0 = Chip operated in Normal mode.
1 = Chip power down Enabled.
[8] HXT_SELXT HXT SELXT
This is a protected register. Please refer to open lock sequence to program it.
0 = High frequency crystal loop back path Disabled. It is used for external oscillator.
1 = High frequency crystal loop back path Enabled. It is used for external crystal.
[9] HXT_CUR_SEL HXT Internal Current Selection
HXT has some internal current path to help crystal start-up.
However when these current path existence, HXT will consume more power.
User can use this bit to balance the start-up and power consumption.
0 = HXT current path always exists. HXT will consume more power.
For 16MHz to 24 MHz crystal.
1 = HXT current path will exist 2ms then cut down. HXT will consume less power.
For 4 MHz to 16 MHz crystal.
[11:10] HXT_GAIN HXT Gain Control Bit
This is a protected register. Please refer to open lock sequence to program it.
Gain control is used to enlarge the gain of crystal to make sure crystal wok normally.
If gain control is enabled, crystal will consume more power than gain control off.
00 = HXT frequency is lower than from 8 MHz.
01 = HXT frequency is from 8 MHz to 12 MHz.
10 = HXT frequency is from 12 MHz to 16 MHz.
11 = HXT frequency is higher than 16 MHz.
[12] HIRC_FSEL HIRC Output Frequency Select
0 = HIRC will output 12MHz clock.
1 = HIRC will output 16MHz Clock.
[13] HIRC_F_STOP HIRC Stop Output When Frequency Changes
This is a protected register. Please refer to open lock sequence to program it.
0 = HIRC will continue to output when HIRC frequency changes.
1 = HIRC will suppress to output during first 16 clocks when HIRC frequency change.

Definition at line 983 of file Nano1X2Series.h.

◆ RESERVE0

uint32_t CLK_T::RESERVE0[1]

Definition at line 1321 of file Nano1X2Series.h.

◆ SP_DET

__IO uint32_t CLK_T::SP_DET

SP_DET

Offset: 0x3C Clock Stop Detect Control Register

Bits Field Descriptions
[0] HCLK_DET HCLK Stop Detect Enable Control
0 = HCLK stop detect Disabled.
1 = HCLK stop detect Enabled.
Once HCLK stop detected, hardware will force HCLK from LIRC.
[1] HCLK_STOP_IE HCLK Stop Detect Interrupt Enable Control
0 = HCLK stop detect interrupt Disabled.
1 = HCLK stop detect interrupt Enabled.
[2] HXT_DET HXT Stop Detect Enable Control
0 = HXT stop detect Disabled.
1 = HXT stop detect Enabled.
[3] HXT_STOP_IE HXT Stop Detect Interrupt Enable Control
0 = HXT stop detect interrupt Disabled.
1 = HXT stop detect interrupt Enabled.
[4] HIRC_DET HIRC Stop Detect Enable Control
0 = HIRC stop detect Disabled.
1 = HIRC stop detect Enabled.
[5] HIRC_STOP_IE HIRC Stop Detect Interrupt Enable Control
0 = HIRC stop detect interrupt Disabled.
1 = HIRC stop detect interrupt Enabled.

Definition at line 1403 of file Nano1X2Series.h.

◆ SP_STS

__I uint32_t CLK_T::SP_STS

SP_STS

Offset: 0x40 Clock Stop Detect Status Register

Bits Field Descriptions
[0] HCLK_SP_IS HCLK Clock Stop Flag
0 = HCLK normal.
1 = HCLK abnormal.
[2] HXT_SP_IS HXT Stop Flag
0 = HXT normal.
1 = HXT abnormal.
[4] HIRC_SP_IS HIRC Stop Flag
0 = HIRC normal.
1 = HIRC abnormal.
[10:8] HCLK_SEL HCLK Target Clock Select
000 = HXT
001 = LXT
010 = PLL Clock
011 = LIRC
111 = HIRC
Others = Reserved

Definition at line 1429 of file Nano1X2Series.h.

◆ WK_INTSTS

__IO uint32_t CLK_T::WK_INTSTS

WK_INTSTS

Offset: 0x30 Wake-up Interrupt Status

Bits Field Descriptions
[0] PD_WK_IS Wake-Up Interrupt Status In Chip Power-Down Mode
This bit indicates that some event resumes chip from Power-down mode
The status is set if external interrupts, UART, GPIO, RTC, USB, SPI, Timer, WDT, and BOD wake-up occurred.
Write 1 to clear this bit.

Definition at line 1336 of file Nano1X2Series.h.


The documentation for this struct was generated from the following file: