NANO102/112 BSP V3.03.003
The Board Support Package for Nano102/112 Series
pdma.h
Go to the documentation of this file.
1/**************************************************************************/
12#ifndef __PDMA_H__
13#define __PDMA_H__
14
15#ifdef __cplusplus
16extern "C"
17{
18#endif
19
20
33/*---------------------------------------------------------------------------------------------------------*/
34/* Data Width Constant Definitions */
35/*---------------------------------------------------------------------------------------------------------*/
36#define PDMA_WIDTH_8 0x00080000UL
37#define PDMA_WIDTH_16 0x00100000UL
38#define PDMA_WIDTH_32 0x00000000UL
40/*---------------------------------------------------------------------------------------------------------*/
41/* Address Attribute Constant Definitions */
42/*---------------------------------------------------------------------------------------------------------*/
43#define PDMA_SAR_INC 0x00000000UL
44#define PDMA_SAR_FIX 0x00000020UL
45#define PDMA_SAR_WRA 0x00000030UL
46#define PDMA_DAR_INC 0x00000000UL
47#define PDMA_DAR_FIX 0x00000080UL
48#define PDMA_DAR_WRA 0x000000C0UL
50/*---------------------------------------------------------------------------------------------------------*/
51/* Peripheral Transfer Mode Constant Definitions */
52/*---------------------------------------------------------------------------------------------------------*/
53#define PDMA_SPI0_TX 0x00000000UL
54#define PDMA_SPI1_TX 0x00000001UL
55#define PDMA_UART0_TX 0x00000002UL
56#define PDMA_UART1_TX 0x00000003UL
57#define PDMA_TMR0_TX 0x00000009UL
58#define PDMA_TMR1_TX 0x0000000AUL
59#define PDMA_TMR2_TX 0x0000000BUL
60#define PDMA_TMR3_TX 0x0000000CUL
62#define PDMA_SPI0_RX 0x00000010UL
63#define PDMA_SPI1_RX 0x00000011UL
64#define PDMA_UART0_RX 0x00000012UL
65#define PDMA_UART1_RX 0x00000013UL
66#define PDMA_ADC 0x00000016UL
67#define PDMA_PWM0_CH0 0x00000019UL
68#define PDMA_PWM0_CH2 0x0000001AUL
69#define PDMA_MEM 0x0000001FUL /* end of group NANO1X2_PDMA_EXPORTED_CONSTANTS */
72
87#define PDMA_GET_INT_STATUS() ((uint32_t)(PDMAGCR->GCRISR))
88
99#define PDMA_GET_CH_INT_STS(u32Ch) (*((__IO uint32_t *)((uint32_t)&PDMA1->ISR + (uint32_t)((u32Ch-1)*0x100))))
100
112#define PDMA_CLR_CH_INT_FLAG(u32Ch, u32Mask) (*((__IO uint32_t *)((uint32_t)&PDMA1->ISR + (uint32_t)((u32Ch-1)*0x100))) = (u32Mask))
113
125#define PDMA_IS_CH_BUSY(u32Ch) ((*((__IO uint32_t *)((uint32_t)&PDMA1->CSR +(uint32_t)((u32Ch-1)*0x100))) & PDMA_CSR_TRIG_EN_Msk)? 1 : 0)
126
138#define PDMA_SET_SRC_ADDR(u32Ch, u32Addr) (*((__IO uint32_t *)((uint32_t)&PDMA1->SAR + (uint32_t)((u32Ch-1)*0x100))) = (u32Addr))
139
151#define PDMA_SET_DST_ADDR(u32Ch, u32Addr) (*((__IO uint32_t *)((uint32_t)&PDMA1->DAR + (uint32_t)((u32Ch-1)*0x100))) = (u32Addr))
152
164#define PDMA_SET_TRANS_CNT(u32Ch, u32Count) { \
165 if (((uint32_t)*((__IO uint32_t *)((uint32_t)&PDMA1->CSR + (uint32_t)((u32Ch-1)*0x100))) & PDMA_CSR_APB_TWS_Msk) == PDMA_WIDTH_32) \
166 *((__IO uint32_t *)((uint32_t)&PDMA1->BCR + (uint32_t)((u32Ch-1)*0x100))) = ((u32Count) << 2); \
167 else if (((uint32_t)*((__IO uint32_t *)((uint32_t)&PDMA1->CSR + (uint32_t)((u32Ch-1)*0x100))) & PDMA_CSR_APB_TWS_Msk) == PDMA_WIDTH_8) \
168 *((__IO uint32_t *)((uint32_t)&PDMA1->BCR + (uint32_t)((u32Ch-1)*0x100))) = (u32Count); \
169 else if (((uint32_t)*((__IO uint32_t *)((uint32_t)&PDMA1->CSR + (uint32_t)((u32Ch-1)*0x100))) & PDMA_CSR_APB_TWS_Msk) == PDMA_WIDTH_16) \
170 *((__IO uint32_t *)((uint32_t)&PDMA1->BCR + (uint32_t)((u32Ch-1)*0x100))) = ((u32Count) << 1); \
171}
172
183#define PDMA_STOP(u32Ch) (*((__IO uint32_t *)((uint32_t)&PDMA1->CSR + (uint32_t)((u32Ch-1)*0x100))) &= ~PDMA_CSR_PDMACEN_Msk)
184
185void PDMA_Open(uint32_t u32Mask);
186void PDMA_Close(void);
187void PDMA_SetTransferCnt(uint32_t u32Ch, uint32_t u32Width, uint32_t u32TransCount);
188void PDMA_SetTransferAddr(uint32_t u32Ch, uint32_t u32SrcAddr, uint32_t u32SrcCtrl, uint32_t u32DstAddr, uint32_t u32DstCtrl);
189void PDMA_SetTransferMode(uint32_t u32Ch, uint32_t u32Periphral, uint32_t u32ScatterEn, uint32_t u32DescAddr);
190void PDMA_SetTimeOut(uint32_t u32Ch, uint32_t u32OnOff, uint32_t u32TimeOutCnt);
191void PDMA_Trigger(uint32_t u32Ch);
192void PDMA_EnableInt(uint32_t u32Ch, uint32_t u32Mask);
193void PDMA_DisableInt(uint32_t u32Ch, uint32_t u32Mask);
194 /* end of group NANO1X2_PDMA_EXPORTED_FUNCTIONS */
196 /* end of group NANO1X2_PDMA_Driver */
198 /* end of group NANO1X2_Device_Driver */
200
201#ifdef __cplusplus
202}
203#endif
204
205#endif //__PDMA_H__
206
207/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
void PDMA_SetTransferAddr(uint32_t u32Ch, uint32_t u32SrcAddr, uint32_t u32SrcCtrl, uint32_t u32DstAddr, uint32_t u32DstCtrl)
Set PDMA Transfer Address.
Definition: pdma.c:105
void PDMA_Trigger(uint32_t u32Ch)
Trigger PDMA.
Definition: pdma.c:191
void PDMA_SetTimeOut(uint32_t u32Ch, uint32_t u32OnOff, uint32_t u32TimeOutCnt)
Set PDMA Timeout.
Definition: pdma.c:172
void PDMA_EnableInt(uint32_t u32Ch, uint32_t u32Mask)
Enable Interrupt.
Definition: pdma.c:209
void PDMA_Open(uint32_t u32Mask)
PDMA Open.
Definition: pdma.c:38
void PDMA_Close(void)
PDMA Close.
Definition: pdma.c:52
void PDMA_DisableInt(uint32_t u32Ch, uint32_t u32Mask)
Disable Interrupt.
Definition: pdma.c:227
void PDMA_SetTransferMode(uint32_t u32Ch, uint32_t u32Periphral, uint32_t u32ScatterEn, uint32_t u32DescAddr)
Set PDMA Transfer Mode.
Definition: pdma.c:131
void PDMA_SetTransferCnt(uint32_t u32Ch, uint32_t u32Width, uint32_t u32TransCount)
Set PDMA Transfer Count.
Definition: pdma.c:68