33#define DAC_WRITE_DAT_TRIGGER (0UL << DAC_CTL_DACLSEL_Pos)
34#define DAC_PDMA_TRIGGER (1UL << DAC_CTL_DACLSEL_Pos)
35#define DAC_TIMER0_TRIGGER (2UL << DAC_CTL_DACLSEL_Pos)
36#define DAC_TIMER1_TRIGGER (3UL << DAC_CTL_DACLSEL_Pos)
37#define DAC_TIMER2_TRIGGER (4UL << DAC_CTL_DACLSEL_Pos)
38#define DAC_TIMER3_TRIGGER (5UL << DAC_CTL_DACLSEL_Pos)
40#define DAC_REFSEL_POWER (0UL << DAC_COMCTL_REFSEL_Pos)
41#define DAC_REFSEL_INT_VREF (1UL << DAC_COMCTL_REFSEL_Pos)
42#define DAC_REFSEL_VREF (2UL << DAC_COMCTL_REFSEL_Pos)
60#define DAC_WRITE_DATA(dac, u32Ch, u32Data) do {\
62 DAC->DATA1 = u32Data;\
64 DAC->DATA0 = u32Data;\
75#define DAC_ENABLE_GROUP_MODE(dac) (DAC->COMCTL |= DAC_COMCTL_DAC01GRP_Msk)
83#define DAC_DISABLE_GROUP_MODE(dac) (DAC->COMCTL &= ~DAC_COMCTL_DAC01GRP_Msk)
95#define DAC_IS_BUSY(dac, u32Ch) (inp32(DAC_BASE + 0x8 + 0x10 * (u32Ch)) & DAC_STS_BUSY_Msk ? 1 : 0)
107#define DAC_GET_INT_FLAG(dac, u32Ch) (inp32(DAC_BASE + 0x8 + 0x10 * (u32Ch)) & DAC_STS_DACIFG_Msk ? 1 : 0)
116#define DAC_CLR_INT_FLAG(dac, u32Ch) do {\
118 DAC->STS1 = DAC_STS_DACIFG_Msk;\
120 DAC->STS0 = DAC_STS_DACIFG_Msk;\
134#define DAC_SET_REF_VOLTAGE(dac, u32Ref) (DAC->COMCTL = ((DAC->COMCTL) & ~DAC_COMCTL_REFSEL_Msk) | u32Ref)
143#define DAC_ENABLE_INT(dac, u32Ch) do {\
145 DAC->CTL1 |= DAC_CTL_DACIE_Msk;\
147 DAC->CTL0 |= DAC_CTL_DACIE_Msk;\
157#define DAC_DISABLE_INT(dac, u32Ch) do {\
159 DAC->CTL1 &= ~DAC_CTL_DACIE_Msk;\
161 DAC->CTL0 &= ~DAC_CTL_DACIE_Msk;\
164void DAC_Open(
DAC_T *dac, uint32_t u32Ch, uint32_t u32TrgSrc);
int DAC_SetDelayTime(DAC_T *dac, uint32_t u32Delay)
Set delay time for DAC to become stable.
void DAC_Close(DAC_T *dac, uint32_t u32Ch)
Disable DAC analog power.
void DAC_Open(DAC_T *dac, uint32_t u32Ch, uint32_t u32TrgSrc)
This function make a DAC channel ready to convert.