M480 BSP V3.05.006
The Board Support Package for M480 Series
uart.c
Go to the documentation of this file.
1/**************************************************************************/
10#include <stdio.h>
11#include "NuMicro.h"
12
41void UART_ClearIntFlag(UART_T* uart, uint32_t u32InterruptFlag)
42{
43
44 if(u32InterruptFlag & UART_INTSTS_RLSINT_Msk) /* Clear Receive Line Status Interrupt */
45 {
48 }
49
50 if(u32InterruptFlag & UART_INTSTS_MODEMINT_Msk) /* Clear Modem Status Interrupt */
51 {
53 }
54 else
55 {
56 }
57
58 if(u32InterruptFlag & UART_INTSTS_BUFERRINT_Msk) /* Clear Buffer Error Interrupt */
59 {
61 }
62
63 if(u32InterruptFlag & UART_INTSTS_WKINT_Msk) /* Clear Wake-up Interrupt */
64 {
68 }
69
70 if(u32InterruptFlag & UART_INTSTS_LININT_Msk) /* Clear LIN Bus Interrupt */
71 {
76 }
77}
78
79
89void UART_Close(UART_T* uart)
90{
91 uart->INTEN = 0ul;
92}
93
94
105{
107}
108
109
128void UART_DisableInt(UART_T* uart, uint32_t u32InterruptFlag)
129{
130 /* Disable UART specified interrupt */
131 UART_DISABLE_INT(uart, u32InterruptFlag);
132}
133
134
145{
146 /* Set RTS pin output is low level active */
148
149 /* Set CTS pin input is low level active */
151
152 /* Set RTS and CTS auto flow control enable */
154}
155
156
175void UART_EnableInt(UART_T* uart, uint32_t u32InterruptFlag)
176{
177 /* Enable UART specified interrupt */
178 UART_ENABLE_INT(uart, u32InterruptFlag);
179}
180
181
192void UART_Open(UART_T* uart, uint32_t u32baudrate)
193{
194 uint32_t u32UartClkSrcSel=0ul, u32UartClkDivNum=0ul;
195 uint32_t u32ClkTbl[4] = {__HXT, 0ul, __LXT, __HIRC};
196 uint32_t u32Baud_Div = 0ul;
197
198
199 if(uart==(UART_T*)UART0)
200 {
201 /* Get UART clock source selection */
202 u32UartClkSrcSel = ((uint32_t)(CLK->CLKSEL1 & CLK_CLKSEL1_UART0SEL_Msk)) >> CLK_CLKSEL1_UART0SEL_Pos;
203 /* Get UART clock divider number */
204 u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART0DIV_Msk) >> CLK_CLKDIV0_UART0DIV_Pos;
205 }
206 else if(uart==(UART_T*)UART1)
207 {
208 /* Get UART clock source selection */
209 u32UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART1SEL_Msk) >> CLK_CLKSEL1_UART1SEL_Pos;
210 /* Get UART clock divider number */
211 u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART1DIV_Msk) >> CLK_CLKDIV0_UART1DIV_Pos;
212 }
213 else if(uart==(UART_T*)UART2)
214 {
215 /* Get UART clock source selection */
216 u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART2SEL_Msk) >> CLK_CLKSEL3_UART2SEL_Pos;
217 /* Get UART clock divider number */
218 u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART2DIV_Msk) >> CLK_CLKDIV4_UART2DIV_Pos;
219 }
220 else if(uart==(UART_T*)UART3)
221 {
222 /* Get UART clock source selection */
223 u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART3SEL_Msk) >> CLK_CLKSEL3_UART3SEL_Pos;
224 /* Get UART clock divider number */
225 u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART3DIV_Msk) >> CLK_CLKDIV4_UART3DIV_Pos;
226 }
227 else if(uart==(UART_T*)UART4)
228 {
229 /* Get UART clock source selection */
230 u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART4SEL_Msk) >> CLK_CLKSEL3_UART4SEL_Pos;
231 /* Get UART clock divider number */
232 u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART4DIV_Msk) >> CLK_CLKDIV4_UART4DIV_Pos;
233 }
234 else if(uart==(UART_T*)UART5)
235 {
236 /* Get UART clock source selection */
237 u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART5SEL_Msk) >> CLK_CLKSEL3_UART5SEL_Pos;
238 /* Get UART clock divider number */
239 u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART5DIV_Msk) >> CLK_CLKDIV4_UART5DIV_Pos;
240 }
241 else if((uart==(UART_T*)UART6) && ((SYS->CSERVER & SYS_CSERVER_VERSION_Msk) == 0x1)) // M480LD
242 {
243 /* Get UART clock source selection */
244 u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART6SEL_Msk) >> CLK_CLKSEL3_UART6SEL_Pos;
245 /* Get UART clock divider number */
246 u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART6DIV_Msk) >> CLK_CLKDIV4_UART6DIV_Pos;
247 }
248 else if((uart==(UART_T*)UART7) && ((SYS->CSERVER & SYS_CSERVER_VERSION_Msk) == 0x1)) // M480LD
249 {
250 /* Get UART clock source selection */
251 u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART7SEL_Msk) >> CLK_CLKSEL3_UART7SEL_Pos;
252 /* Get UART clock divider number */
253 u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART7DIV_Msk) >> CLK_CLKDIV4_UART7DIV_Pos;
254 }
255
256 /* Select UART function */
258
259 /* Set UART line configuration */
261
262 /* Set UART Rx and RTS trigger level */
264
265 /* Get PLL clock frequency if UART clock source selection is PLL */
266 if(u32UartClkSrcSel == 1ul)
267 {
268 u32ClkTbl[u32UartClkSrcSel] = CLK_GetPLLClockFreq();
269 }
270
271 /* Set UART baud rate */
272 if(u32baudrate != 0ul)
273 {
274 u32Baud_Div = UART_BAUD_MODE2_DIVIDER((u32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32baudrate);
275
276 if(u32Baud_Div > 0xFFFFul)
277 {
278 uart->BAUD = (UART_BAUD_MODE0 | UART_BAUD_MODE0_DIVIDER((u32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32baudrate));
279 }
280 else
281 {
282 uart->BAUD = (UART_BAUD_MODE2 | u32Baud_Div);
283 }
284 }
285}
286
287
299uint32_t UART_Read(UART_T* uart, uint8_t pu8RxBuf[], uint32_t u32ReadBytes)
300{
301 uint32_t u32Count, u32delayno;
302 uint32_t u32Exit = 0ul;
303
304 for(u32Count = 0ul; u32Count < u32ReadBytes; u32Count++)
305 {
306 u32delayno = 0ul;
307
308 while(uart->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk) /* Check RX empty => failed */
309 {
310 u32delayno++;
311 if(u32delayno >= 0x40000000ul)
312 {
313 u32Exit = 1ul;
314 break;
315 }
316 else
317 {
318 }
319 }
320
321 if(u32Exit == 1ul)
322 {
323 break;
324 }
325 else
326 {
327 pu8RxBuf[u32Count] = (uint8_t)uart->DAT; /* Get Data from UART RX */
328 }
329 }
330
331 return u32Count;
332
333}
334
335
362void UART_SetLineConfig(UART_T* uart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t u32stop_bits)
363{
364 uint32_t u32UartClkSrcSel=0ul, u32UartClkDivNum=0ul;
365 uint32_t u32ClkTbl[4ul] = {__HXT, 0ul, __LXT, __HIRC};
366 uint32_t u32Baud_Div = 0ul;
367
368
369 if(uart==(UART_T*)UART0)
370 {
371 /* Get UART clock source selection */
372 u32UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART0SEL_Msk) >> CLK_CLKSEL1_UART0SEL_Pos;
373 /* Get UART clock divider number */
374 u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART0DIV_Msk) >> CLK_CLKDIV0_UART0DIV_Pos;
375 }
376 else if(uart==(UART_T*)UART1)
377 {
378 /* Get UART clock source selection */
379 u32UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART1SEL_Msk) >> CLK_CLKSEL1_UART1SEL_Pos;
380 /* Get UART clock divider number */
381 u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART1DIV_Msk) >> CLK_CLKDIV0_UART1DIV_Pos;
382 }
383 else if(uart==(UART_T*)UART2)
384 {
385 /* Get UART clock source selection */
386 u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART2SEL_Msk) >> CLK_CLKSEL3_UART2SEL_Pos;
387 /* Get UART clock divider number */
388 u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART2DIV_Msk) >> CLK_CLKDIV4_UART2DIV_Pos;
389 }
390 else if(uart==(UART_T*)UART3)
391 {
392 /* Get UART clock source selection */
393 u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART3SEL_Msk) >> CLK_CLKSEL3_UART3SEL_Pos;
394 /* Get UART clock divider number */
395 u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART3DIV_Msk) >> CLK_CLKDIV4_UART3DIV_Pos;
396 }
397 else if(uart==(UART_T*)UART4)
398 {
399 /* Get UART clock source selection */
400 u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART4SEL_Msk) >> CLK_CLKSEL3_UART4SEL_Pos;
401 /* Get UART clock divider number */
402 u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART4DIV_Msk) >> CLK_CLKDIV4_UART4DIV_Pos;
403 }
404 else if(uart==(UART_T*)UART5)
405 {
406 /* Get UART clock source selection */
407 u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART5SEL_Msk) >> CLK_CLKSEL3_UART5SEL_Pos;
408 /* Get UART clock divider number */
409 u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART5DIV_Msk) >> CLK_CLKDIV4_UART5DIV_Pos;
410 }
411 else if((uart==(UART_T*)UART6) && ((SYS->CSERVER & SYS_CSERVER_VERSION_Msk) == 0x1)) // M480LD
412 {
413 /* Get UART clock source selection */
414 u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART6SEL_Msk) >> CLK_CLKSEL3_UART6SEL_Pos;
415 /* Get UART clock divider number */
416 u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART6DIV_Msk) >> CLK_CLKDIV4_UART6DIV_Pos;
417 }
418 else if((uart==(UART_T*)UART7) && ((SYS->CSERVER & SYS_CSERVER_VERSION_Msk) == 0x1)) // M480LD
419 {
420 /* Get UART clock source selection */
421 u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART7SEL_Msk) >> CLK_CLKSEL3_UART7SEL_Pos;
422 /* Get UART clock divider number */
423 u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART7DIV_Msk) >> CLK_CLKDIV4_UART7DIV_Pos;
424 }
425
426 /* Get PLL clock frequency if UART clock source selection is PLL */
427 if(u32UartClkSrcSel == 1ul)
428 {
429 u32ClkTbl[u32UartClkSrcSel] = CLK_GetPLLClockFreq();
430 }
431 else
432 {
433 }
434
435 /* Set UART baud rate */
436 if(u32baudrate != 0ul)
437 {
438 u32Baud_Div = UART_BAUD_MODE2_DIVIDER((u32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32baudrate);
439
440 if(u32Baud_Div > 0xFFFFul)
441 {
442 uart->BAUD = (UART_BAUD_MODE0 | UART_BAUD_MODE0_DIVIDER((u32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32baudrate));
443 }
444 else
445 {
446 uart->BAUD = (UART_BAUD_MODE2 | u32Baud_Div);
447 }
448 }
449
450 /* Set UART line configuration */
451 uart->LINE = u32data_width | u32parity | u32stop_bits;
452}
453
454
465void UART_SetTimeoutCnt(UART_T* uart, uint32_t u32TOC)
466{
467 /* Set time-out interrupt comparator */
468 uart->TOUT = (uart->TOUT & ~UART_TOUT_TOIC_Msk) | (u32TOC);
469
470 /* Set time-out counter enable */
472}
473
474
488void UART_SelectIrDAMode(UART_T* uart, uint32_t u32Buadrate, uint32_t u32Direction)
489{
490 uint32_t u32UartClkSrcSel=0ul, u32UartClkDivNum=0ul;
491 uint32_t u32ClkTbl[4ul] = {__HXT, 0ul, __LXT, __HIRC};
492 uint32_t u32Baud_Div;
493
494 /* Select IrDA function mode */
496
497
498 if(uart==UART0)
499 {
500 /* Get UART clock source selection */
501 u32UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART0SEL_Msk) >> CLK_CLKSEL1_UART0SEL_Pos;
502 /* Get UART clock divider number */
503 u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART0DIV_Msk) >> CLK_CLKDIV0_UART0DIV_Pos;
504 }
505 else if(uart==UART1)
506 {
507 /* Get UART clock source selection */
508 u32UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART1SEL_Msk) >> CLK_CLKSEL1_UART1SEL_Pos;
509 /* Get UART clock divider number */
510 u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART1DIV_Msk) >> CLK_CLKDIV0_UART1DIV_Pos;
511 }
512 else if(uart==UART2)
513 {
514 /* Get UART clock source selection */
515 u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART2SEL_Msk) >> CLK_CLKSEL3_UART2SEL_Pos;
516 /* Get UART clock divider number */
517 u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART2DIV_Msk) >> CLK_CLKDIV4_UART2DIV_Pos;
518 }
519 else if(uart==UART3)
520 {
521 /* Get UART clock source selection */
522 u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART3SEL_Msk) >> CLK_CLKSEL3_UART3SEL_Pos;
523 /* Get UART clock divider number */
524 u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART3DIV_Msk) >> CLK_CLKDIV4_UART3DIV_Pos;
525 }
526 else if(uart==UART4)
527 {
528 /* Get UART clock source selection */
529 u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART4SEL_Msk) >> CLK_CLKSEL3_UART4SEL_Pos;
530 /* Get UART clock divider number */
531 u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART4DIV_Msk) >> CLK_CLKDIV4_UART4DIV_Pos;
532 }
533 else if(uart==UART5)
534 {
535 /* Get UART clock source selection */
536 u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART5SEL_Msk) >> CLK_CLKSEL3_UART5SEL_Pos;
537 /* Get UART clock divider number */
538 u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART5DIV_Msk) >> CLK_CLKDIV4_UART5DIV_Pos;
539 }
540 else if((uart==(UART_T*)UART6) && ((SYS->CSERVER & SYS_CSERVER_VERSION_Msk) == 0x1)) // M480LD
541 {
542 /* Get UART clock source selection */
543 u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART6SEL_Msk) >> CLK_CLKSEL3_UART6SEL_Pos;
544 /* Get UART clock divider number */
545 u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART6DIV_Msk) >> CLK_CLKDIV4_UART6DIV_Pos;
546 }
547 else if((uart==(UART_T*)UART7) && ((SYS->CSERVER & SYS_CSERVER_VERSION_Msk) == 0x1)) // M480LD
548 {
549 /* Get UART clock source selection */
550 u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART7SEL_Msk) >> CLK_CLKSEL3_UART7SEL_Pos;
551 /* Get UART clock divider number */
552 u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART7DIV_Msk) >> CLK_CLKDIV4_UART7DIV_Pos;
553 }
554
555 /* Get PLL clock frequency if UART clock source selection is PLL */
556 if(u32UartClkSrcSel == 1ul)
557 {
558 u32ClkTbl[u32UartClkSrcSel] = CLK_GetPLLClockFreq();
559 }
560 else
561 {
562 }
563
564 /* Set UART IrDA baud rate in mode 0 */
565 if(u32Buadrate != 0ul)
566 {
567 u32Baud_Div = UART_BAUD_MODE0_DIVIDER((u32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32Buadrate);
568
569 if(u32Baud_Div < 0xFFFFul)
570 {
571 uart->BAUD = (UART_BAUD_MODE0 | u32Baud_Div);
572 }
573 else
574 {
575 }
576 }
577
578 /* Configure IrDA relative settings */
579 if(u32Direction == UART_IRDA_RXEN)
580 {
581 uart->IRDA |= UART_IRDA_RXINV_Msk; /*Rx signal is inverse*/
582 uart->IRDA &= ~UART_IRDA_TXEN_Msk;
583 }
584 else
585 {
586 uart->IRDA &= ~UART_IRDA_TXINV_Msk; /*Tx signal is not inverse*/
587 uart->IRDA |= UART_IRDA_TXEN_Msk;
588 }
589
590}
591
592
607void UART_SelectRS485Mode(UART_T* uart, uint32_t u32Mode, uint32_t u32Addr)
608{
609 /* Select UART RS485 function mode */
611
612 /* Set RS585 configuration */
614 uart->ALTCTL |= (u32Mode | (u32Addr << UART_ALTCTL_ADDRMV_Pos));
615}
616
617
631void UART_SelectLINMode(UART_T* uart, uint32_t u32Mode, uint32_t u32BreakLength)
632{
633 /* Select LIN function mode */
635
636 /* Select LIN function setting : Tx enable, Rx enable and break field length */
638 uart->ALTCTL |= (u32Mode | (u32BreakLength << UART_ALTCTL_BRKFL_Pos));
639}
640
641
653uint32_t UART_Write(UART_T* uart, uint8_t pu8TxBuf[], uint32_t u32WriteBytes)
654{
655 uint32_t u32Count, u32delayno;
656 uint32_t u32Exit = 0ul;
657
658 for(u32Count = 0ul; u32Count != u32WriteBytes; u32Count++)
659 {
660 u32delayno = 0ul;
661 while(uart->FIFOSTS & UART_FIFOSTS_TXFULL_Msk) /* Check Tx Full */
662 {
663 u32delayno++;
664 if(u32delayno >= 0x40000000ul)
665 {
666 u32Exit = 1ul;
667 break;
668 }
669 else
670 {
671 }
672 }
673
674 if(u32Exit == 1ul)
675 {
676 break;
677 }
678 else
679 {
680 uart->DAT = pu8TxBuf[u32Count]; /* Send UART Data from buffer */
681 }
682 }
683
684 return u32Count;
685}
686
687 /* end of group UART_EXPORTED_FUNCTIONS */
689 /* end of group UART_Driver */
691 /* end of group Standard_Driver */
693
694/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
695
696
697
NuMicro peripheral access layer header file.
uint32_t CLK_GetPLLClockFreq(void)
Get PLL clock frequency.
Definition: clk.c:1201
#define UART0
Definition: M480.h:429
#define UART7
Definition: M480.h:436
#define CLK
Definition: M480.h:368
#define UART6
Definition: M480.h:435
#define UART4
Definition: M480.h:433
#define UART2
Definition: M480.h:431
#define UART1
Definition: M480.h:430
#define UART5
Definition: M480.h:434
#define UART3
Definition: M480.h:432
#define SYS
Definition: M480.h:367
#define CLK_CLKDIV4_UART4DIV_Pos
Definition: clk_reg.h:2666
#define UART_FIFOSTS_BIF_Msk
Definition: uart_reg.h:1979
#define SYS_CSERVER_VERSION_Msk
Definition: sys_reg.h:6034
#define CLK_CLKSEL1_UART0SEL_Msk
Definition: clk_reg.h:2541
#define UART_FIFOSTS_TXOVIF_Msk
Definition: uart_reg.h:2000
#define UART_FIFOSTS_RXOVIF_Msk
Definition: uart_reg.h:1961
#define CLK_CLKDIV4_UART5DIV_Msk
Definition: clk_reg.h:2670
#define CLK_CLKDIV0_UART1DIV_Pos
Definition: clk_reg.h:2624
#define CLK_CLKSEL3_UART5SEL_Msk
Definition: clk_reg.h:2613
#define CLK_CLKDIV4_UART3DIV_Msk
Definition: clk_reg.h:2664
#define UART_ALTCTL_LINTXEN_Msk
Definition: uart_reg.h:2126
#define UART_INTEN_ATORTSEN_Msk
Definition: uart_reg.h:1883
#define CLK_CLKSEL1_UART1SEL_Msk
Definition: clk_reg.h:2544
#define CLK_CLKDIV4_UART6DIV_Msk
Definition: clk_reg.h:2673
#define CLK_CLKSEL3_UART7SEL_Msk
Definition: clk_reg.h:2601
#define UART_INTSTS_BUFERRINT_Msk
Definition: uart_reg.h:2051
#define UART_WKSTS_DATWKF_Msk
Definition: uart_reg.h:2243
#define UART_ALTCTL_ADDRMV_Msk
Definition: uart_reg.h:2150
#define CLK_CLKDIV4_UART2DIV_Pos
Definition: clk_reg.h:2660
#define CLK_CLKSEL3_UART4SEL_Msk
Definition: clk_reg.h:2610
#define UART_FIFOSTS_TXFULL_Msk
Definition: uart_reg.h:1997
#define CLK_CLKDIV4_UART7DIV_Msk
Definition: clk_reg.h:2676
#define UART_ALTCTL_ADDRMV_Pos
Definition: uart_reg.h:2149
#define UART_LINSTS_SLVHEF_Msk
Definition: uart_reg.h:2204
#define UART_INTSTS_LINIF_Msk
Definition: uart_reg.h:2033
#define UART_FIFOSTS_ADDRDETF_Msk
Definition: uart_reg.h:1970
#define UART_ALTCTL_RS485AUD_Msk
Definition: uart_reg.h:2135
#define CLK_CLKDIV0_UART1DIV_Msk
Definition: clk_reg.h:2625
#define CLK_CLKDIV4_UART2DIV_Msk
Definition: clk_reg.h:2661
#define CLK_CLKDIV4_UART4DIV_Msk
Definition: clk_reg.h:2667
#define UART_ALTCTL_BRKFL_Pos
Definition: uart_reg.h:2119
#define UART_IRDA_RXINV_Msk
Definition: uart_reg.h:2117
#define UART_ALTCTL_LINRXEN_Msk
Definition: uart_reg.h:2123
#define UART_FIFO_RFITL_Msk
Definition: uart_reg.h:1907
#define UART_LINSTS_SLVHDETF_Msk
Definition: uart_reg.h:2201
#define UART_INTSTS_MODEMINT_Msk
Definition: uart_reg.h:2045
#define CLK_CLKSEL3_UART2SEL_Pos
Definition: clk_reg.h:2603
#define UART_LINSTS_BRKDETF_Msk
Definition: uart_reg.h:2213
#define CLK_CLKDIV4_UART3DIV_Pos
Definition: clk_reg.h:2663
#define UART_INTEN_ATOCTSEN_Msk
Definition: uart_reg.h:1886
#define CLK_CLKSEL3_UART3SEL_Msk
Definition: clk_reg.h:2607
#define UART_INTSTS_RLSINT_Msk
Definition: uart_reg.h:2042
#define UART_LINSTS_SLVSYNCF_Msk
Definition: uart_reg.h:2210
#define UART_WKSTS_TOUTWKF_Msk
Definition: uart_reg.h:2252
#define CLK_CLKSEL3_UART6SEL_Pos
Definition: clk_reg.h:2597
#define UART_MODEM_RTSACTLV_Msk
Definition: uart_reg.h:1946
#define UART_INTSTS_LININT_Msk
Definition: uart_reg.h:2057
#define CLK_CLKDIV4_UART5DIV_Pos
Definition: clk_reg.h:2669
#define UART_ALTCTL_RS485NMM_Msk
Definition: uart_reg.h:2129
#define UART_WKSTS_CTSWKF_Msk
Definition: uart_reg.h:2240
#define CLK_CLKSEL1_UART1SEL_Pos
Definition: clk_reg.h:2543
#define UART_LINSTS_BITEF_Msk
Definition: uart_reg.h:2216
#define UART_FIFOSTS_RXEMPTY_Msk
Definition: uart_reg.h:1985
#define UART_FIFOSTS_PEF_Msk
Definition: uart_reg.h:1973
#define CLK_CLKSEL1_UART0SEL_Pos
Definition: clk_reg.h:2540
#define CLK_CLKSEL3_UART5SEL_Pos
Definition: clk_reg.h:2612
#define UART_MODEMSTS_CTSDETF_Msk
Definition: uart_reg.h:1952
#define UART_FIFOSTS_FEF_Msk
Definition: uart_reg.h:1976
#define CLK_CLKDIV0_UART0DIV_Pos
Definition: clk_reg.h:2621
#define CLK_CLKDIV4_UART6DIV_Pos
Definition: clk_reg.h:2672
#define UART_LINSTS_SLVIDPEF_Msk
Definition: uart_reg.h:2207
#define CLK_CLKSEL3_UART7SEL_Pos
Definition: clk_reg.h:2600
#define CLK_CLKDIV4_UART7DIV_Pos
Definition: clk_reg.h:2675
#define CLK_CLKSEL3_UART3SEL_Pos
Definition: clk_reg.h:2606
#define UART_WKSTS_RFRTWKF_Msk
Definition: uart_reg.h:2246
#define UART_FIFO_RTSTRGLV_Msk
Definition: uart_reg.h:1913
#define CLK_CLKSEL3_UART4SEL_Pos
Definition: clk_reg.h:2609
#define CLK_CLKDIV0_UART0DIV_Msk
Definition: clk_reg.h:2622
#define UART_INTSTS_WKINT_Msk
Definition: uart_reg.h:2054
#define CLK_CLKSEL3_UART6SEL_Msk
Definition: clk_reg.h:2598
#define UART_ALTCTL_BRKFL_Msk
Definition: uart_reg.h:2120
#define UART_ALTCTL_RS485AAD_Msk
Definition: uart_reg.h:2132
#define UART_IRDA_TXEN_Msk
Definition: uart_reg.h:2111
#define UART_MODEMSTS_CTSACTLV_Msk
Definition: uart_reg.h:1958
#define UART_INTEN_TOCNTEN_Msk
Definition: uart_reg.h:1880
#define CLK_CLKSEL3_UART2SEL_Msk
Definition: clk_reg.h:2604
#define UART_WKSTS_RS485WKF_Msk
Definition: uart_reg.h:2249
#define UART_BAUD_MODE2
Definition: uart.h:113
#define UART_PARITY_NONE
Definition: uart.h:64
#define UART_BAUD_MODE0
Definition: uart.h:112
#define UART_IRDA_RXEN
Definition: uart.h:86
#define UART_FUNCSEL_IrDA
Definition: uart.h:94
#define UART_STOP_BIT_1
Definition: uart.h:70
#define UART_WORD_LEN_8
Definition: uart.h:62
#define UART_FUNCSEL_RS485
Definition: uart.h:95
#define UART_FUNCSEL_UART
Definition: uart.h:92
#define UART_FUNCSEL_LIN
Definition: uart.h:93
void UART_SelectRS485Mode(UART_T *uart, uint32_t u32Mode, uint32_t u32Addr)
Select and configure RS485 function.
Definition: uart.c:607
void UART_SelectLINMode(UART_T *uart, uint32_t u32Mode, uint32_t u32BreakLength)
Select and configure LIN function.
Definition: uart.c:631
void UART_EnableInt(UART_T *uart, uint32_t u32InterruptFlag)
The function is used to enable UART specified interrupt and enable NVIC UART IRQ.
Definition: uart.c:175
uint32_t UART_Write(UART_T *uart, uint8_t pu8TxBuf[], uint32_t u32WriteBytes)
Write UART data.
Definition: uart.c:653
void UART_SetTimeoutCnt(UART_T *uart, uint32_t u32TOC)
Set Rx timeout count.
Definition: uart.c:465
void UART_Close(UART_T *uart)
Disable UART interrupt.
Definition: uart.c:89
#define UART_BAUD_MODE0_DIVIDER(u32SrcFreq, u32BaudRate)
Calculate UART baudrate mode0 divider.
Definition: uart.h:135
#define UART_DISABLE_INT(uart, u32eIntSel)
Disable specified UART interrupt.
Definition: uart.h:348
void UART_ClearIntFlag(UART_T *uart, uint32_t u32InterruptFlag)
Clear UART specified interrupt flag.
Definition: uart.c:41
void UART_DisableFlowCtrl(UART_T *uart)
Disable UART auto flow control function.
Definition: uart.c:104
void UART_EnableFlowCtrl(UART_T *uart)
Enable UART auto flow control function.
Definition: uart.c:144
#define UART_BAUD_MODE2_DIVIDER(u32SrcFreq, u32BaudRate)
Calculate UART baudrate mode2 divider.
Definition: uart.h:149
void UART_SetLineConfig(UART_T *uart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t u32stop_bits)
Set UART line configuration.
Definition: uart.c:362
void UART_DisableInt(UART_T *uart, uint32_t u32InterruptFlag)
Disable UART specified interrupt.
Definition: uart.c:128
void UART_SelectIrDAMode(UART_T *uart, uint32_t u32Buadrate, uint32_t u32Direction)
Select and configure IrDA function.
Definition: uart.c:488
uint32_t UART_Read(UART_T *uart, uint8_t pu8RxBuf[], uint32_t u32ReadBytes)
Read UART data.
Definition: uart.c:299
void UART_Open(UART_T *uart, uint32_t u32baudrate)
Open and set UART function.
Definition: uart.c:192
#define UART_ENABLE_INT(uart, u32eIntSel)
Enable specified UART interrupt.
Definition: uart.h:325
__IO uint32_t DAT
Definition: uart_reg.h:1822
__IO uint32_t INTEN
Definition: uart_reg.h:1823
__IO uint32_t FIFOSTS
Definition: uart_reg.h:1828
__IO uint32_t ALTCTL
Definition: uart_reg.h:1833
__IO uint32_t FUNCSEL
Definition: uart_reg.h:1834
__IO uint32_t BAUD
Definition: uart_reg.h:1831
__IO uint32_t WKSTS
Definition: uart_reg.h:1839
__IO uint32_t LINSTS
Definition: uart_reg.h:1836
__IO uint32_t FIFO
Definition: uart_reg.h:1824
__IO uint32_t MODEM
Definition: uart_reg.h:1826
__IO uint32_t MODEMSTS
Definition: uart_reg.h:1827
__IO uint32_t TOUT
Definition: uart_reg.h:1830
__IO uint32_t IRDA
Definition: uart_reg.h:1832
__IO uint32_t INTSTS
Definition: uart_reg.h:1829
__IO uint32_t LINE
Definition: uart_reg.h:1825
#define __HIRC
Definition: system_M480.h:36
#define __HXT
Definition: system_M480.h:29
#define __LXT
Definition: system_M480.h:33