M480 BSP
V3.05.006
The Board Support Package for M480 Series
Device
Nuvoton
M480
Include
spim_reg.h
Go to the documentation of this file.
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/**************************************************************************/
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#ifndef __SPIM_REG_H__
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#define __SPIM_REG_H__
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#if defined ( __CC_ARM )
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#pragma anon_unions
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#endif
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typedef
struct
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{
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__IO uint32_t
CTL0
;
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__IO uint32_t
CTL1
;
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__I uint32_t RESERVE0[1];
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__IO uint32_t
RXCLKDLY
;
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__I uint32_t RX[4];
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__IO uint32_t TX[4];
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__IO uint32_t
SRAMADDR
;
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__IO uint32_t
DMACNT
;
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__IO uint32_t
FADDR
;
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__O uint32_t
KEY1
;
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__O uint32_t
KEY2
;
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__IO uint32_t
DMMCTL
;
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__IO uint32_t
CTL2
;
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}
SPIM_T
;
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#define SPIM_CTL0_CIPHOFF_Pos (0)
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#define SPIM_CTL0_CIPHOFF_Msk (0x1ul << SPIM_CTL0_CIPHOFF_Pos)
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#define SPIM_CTL0_BALEN_Pos (2)
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#define SPIM_CTL0_BALEN_Msk (0x1ul << SPIM_CTL0_BALEN_Pos)
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#define SPIM_CTL0_B4ADDREN_Pos (5)
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#define SPIM_CTL0_B4ADDREN_Msk (0x1ul << SPIM_CTL0_B4ADDREN_Pos)
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#define SPIM_CTL0_IEN_Pos (6)
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#define SPIM_CTL0_IEN_Msk (0x1ul << SPIM_CTL0_IEN_Pos)
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#define SPIM_CTL0_IF_Pos (7)
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#define SPIM_CTL0_IF_Msk (0x1ul << SPIM_CTL0_IF_Pos)
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#define SPIM_CTL0_DWIDTH_Pos (8)
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#define SPIM_CTL0_DWIDTH_Msk (0x1ful << SPIM_CTL0_DWIDTH_Pos)
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#define SPIM_CTL0_BURSTNUM_Pos (13)
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#define SPIM_CTL0_BURSTNUM_Msk (0x3ul << SPIM_CTL0_BURSTNUM_Pos)
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#define SPIM_CTL0_QDIODIR_Pos (15)
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#define SPIM_CTL0_QDIODIR_Msk (0x1ul << SPIM_CTL0_QDIODIR_Pos)
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#define SPIM_CTL0_SUSPITV_Pos (16)
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#define SPIM_CTL0_SUSPITV_Msk (0xful << SPIM_CTL0_SUSPITV_Pos)
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#define SPIM_CTL0_BITMODE_Pos (20)
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#define SPIM_CTL0_BITMODE_Msk (0x3ul << SPIM_CTL0_BITMODE_Pos)
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#define SPIM_CTL0_OPMODE_Pos (22)
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#define SPIM_CTL0_OPMODE_Msk (0x3ul << SPIM_CTL0_OPMODE_Pos)
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#define SPIM_CTL0_CMDCODE_Pos (24)
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#define SPIM_CTL0_CMDCODE_Msk (0xfful << SPIM_CTL0_CMDCODE_Pos)
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#define SPIM_CTL1_SPIMEN_Pos (0)
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#define SPIM_CTL1_SPIMEN_Msk (0x1ul << SPIM_CTL1_SPIMEN_Pos)
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#define SPIM_CTL1_CACHEOFF_Pos (1)
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#define SPIM_CTL1_CACHEOFF_Msk (0x1ul << SPIM_CTL1_CACHEOFF_Pos)
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#define SPIM_CTL1_CCMEN_Pos (2)
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#define SPIM_CTL1_CCMEN_Msk (0x1ul << SPIM_CTL1_CCMEN_Pos)
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#define SPIM_CTL1_CDINVAL_Pos (3)
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#define SPIM_CTL1_CDINVAL_Msk (0x1ul << SPIM_CTL1_CDINVAL_Pos)
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#define SPIM_CTL1_SS_Pos (4)
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#define SPIM_CTL1_SS_Msk (0x1ul << SPIM_CTL1_SS_Pos)
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#define SPIM_CTL1_SSACTPOL_Pos (5)
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#define SPIM_CTL1_SSACTPOL_Msk (0x1ul << SPIM_CTL1_SSACTPOL_Pos)
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#define SPIM_CTL1_IDLETIME_Pos (8)
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#define SPIM_CTL1_IDLETIME_Msk (0xful << SPIM_CTL1_IDLETIME_Pos)
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#define SPIM_CTL1_DIVIDER_Pos (16)
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#define SPIM_CTL1_DIVIDER_Msk (0xfffful << SPIM_CTL1_DIVIDER_Pos)
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#define SPIM_RXCLKDLY_DWDELSEL_Pos (0)
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#define SPIM_RXCLKDLY_DWDELSEL_Msk (0xfful << SPIM_RXCLKDLY_DWDELSEL_Pos)
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#define SPIM_RXCLKDLY_RDDLYSEL_Pos (16)
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#define SPIM_RXCLKDLY_RDDLYSEL_Msk (0x7ul << SPIM_RXCLKDLY_RDDLYSEL_Pos)
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#define SPIM_RXCLKDLY_RDEDGE_Pos (20)
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#define SPIM_RXCLKDLY_RDEDGE_Msk (0x1ul << SPIM_RXCLKDLY_RDEDGE_Pos)
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#define SPIM_RX_RXDAT_Pos (0)
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#define SPIM_RX_RXDAT_Msk (0xfffffffful << SPIM_RX_RXDAT_Pos)
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#define SPIM_TX_TXDAT_Pos (0)
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#define SPIM_TX_TXDAT_Msk (0xfffffffful << SPIM_TX_TXDAT_Pos)
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#define SPIM_SRAMADDR_ADDR_Pos (0)
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#define SPIM_SRAMADDR_ADDR_Msk (0xfffffffful << SPIM_SRAMADDR_ADDR_Pos)
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#define SPIM_DMACNT_DMACNT_Pos (0)
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#define SPIM_DMACNT_DMACNT_Msk (0xfffffful << SPIM_DMACNT_DMACNT_Pos)
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#define SPIM_FADDR_ADDR_Pos (0)
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#define SPIM_FADDR_ADDR_Msk (0xfffffffful << SPIM_FADDR_ADDR_Pos)
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#define SPIM_KEY1_KEY1_Pos (0)
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#define SPIM_KEY1_KEY1_Msk (0xfffffffful << SPIM_KEY1_KEY1_Pos)
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#define SPIM_KEY2_KEY2_Pos (0)
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#define SPIM_KEY2_KEY2_Msk (0xfffffffful << SPIM_KEY2_KEY2_Pos)
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#define SPIM_DMMCTL_CRMDAT_Pos (8)
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#define SPIM_DMMCTL_CRMDAT_Msk (0xfful << SPIM_DMMCTL_CRMDAT_Pos)
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#define SPIM_DMMCTL_DESELTIM_Pos (16)
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#define SPIM_DMMCTL_DESELTIM_Msk (0x1ful << SPIM_DMMCTL_DESELTIM_Pos)
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#define SPIM_DMMCTL_BWEN_Pos (24)
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#define SPIM_DMMCTL_BWEN_Msk (0x1ul << SPIM_DMMCTL_BWEN_Pos)
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#define SPIM_DMMCTL_CREN_Pos (25)
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#define SPIM_DMMCTL_CREN_Msk (0x1ul << SPIM_DMMCTL_CREN_Pos)
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#define SPIM_DMMCTL_UACTSCLK_Pos (26)
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#define SPIM_DMMCTL_UACTSCLK_Msk (0x1ul << SPIM_DMMCTL_UACTSCLK_Pos)
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#define SPIM_DMMCTL_ACTSCLKT_Pos (28)
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#define SPIM_DMMCTL_ACTSCLKT_Msk (0xful << SPIM_DMMCTL_ACTSCLKT_Pos)
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#define SPIM_CTL2_USETEN_Pos (16)
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#define SPIM_CTL2_USETEN_Msk (0x1ul << SPIM_CTL2_USETEN_Pos)
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#define SPIM_CTL2_DTRMPOFF_Pos (20)
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#define SPIM_CTL2_DTRMPOFF_Msk (0x1ul << SPIM_CTL2_DTRMPOFF_Pos)
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#define SPIM_CTL2_DCNUM_Pos (24)
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#define SPIM_CTL2_DCNUM_Msk (0x1ful << SPIM_CTL2_DCNUM_Pos)
/* SPIM_CONST */
/* end of SPIM register group */
/* end of REGISTER group */
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#if defined ( __CC_ARM )
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#pragma no_anon_unions
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#endif
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#endif
/* __SPIM_REG_H__ */
SPIM_T
Definition:
spim_reg.h:27
SPIM_T::SRAMADDR
__IO uint32_t SRAMADDR
Definition:
spim_reg.h:870
SPIM_T::CTL2
__IO uint32_t CTL2
Definition:
spim_reg.h:876
SPIM_T::DMMCTL
__IO uint32_t DMMCTL
Definition:
spim_reg.h:875
SPIM_T::KEY2
__O uint32_t KEY2
Definition:
spim_reg.h:874
SPIM_T::CTL1
__IO uint32_t CTL1
Definition:
spim_reg.h:863
SPIM_T::FADDR
__IO uint32_t FADDR
Definition:
spim_reg.h:872
SPIM_T::RXCLKDLY
__IO uint32_t RXCLKDLY
Definition:
spim_reg.h:867
SPIM_T::DMACNT
__IO uint32_t DMACNT
Definition:
spim_reg.h:871
SPIM_T::CTL0
__IO uint32_t CTL0
Definition:
spim_reg.h:862
SPIM_T::KEY1
__O uint32_t KEY1
Definition:
spim_reg.h:873
Generated on Fri Jan 12 2024 10:46:53 for M480 BSP by
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