M480 BSP V3.05.006
The Board Support Package for M480 Series
Data Fields
EPWM_T Struct Reference

#include <epwm_reg.h>

Data Fields

__IO uint32_t CTL0
 
__IO uint32_t CTL1
 
__IO uint32_t SYNC
 
__IO uint32_t SWSYNC
 
__IO uint32_t CLKSRC
 
__IO uint32_t CLKPSC [3]
 
__IO uint32_t CNTEN
 
__IO uint32_t CNTCLR
 
__IO uint32_t LOAD
 
__IO uint32_t PERIOD [6]
 
__IO uint32_t CMPDAT [6]
 
__IO uint32_t DTCTL [3]
 
__IO uint32_t PHS [3]
 
__I uint32_t CNT [6]
 
__IO uint32_t WGCTL0
 
__IO uint32_t WGCTL1
 
__IO uint32_t MSKEN
 
__IO uint32_t MSK
 
__IO uint32_t BNF
 
__IO uint32_t FAILBRK
 
__IO uint32_t BRKCTL [3]
 
__IO uint32_t POLCTL
 
__IO uint32_t POEN
 
__O uint32_t SWBRK
 
__IO uint32_t INTEN0
 
__IO uint32_t INTEN1
 
__IO uint32_t INTSTS0
 
__IO uint32_t INTSTS1
 
__IO uint32_t DACTRGEN
 
__IO uint32_t EADCTS0
 
__IO uint32_t EADCTS1
 
__IO uint32_t FTCMPDAT [3]
 
__IO uint32_t SSCTL
 
__O uint32_t SSTRG
 
__IO uint32_t LEBCTL
 
__IO uint32_t LEBCNT
 
__IO uint32_t STATUS
 
__IO uint32_t IFA [6]
 
__IO uint32_t AINTSTS
 
__IO uint32_t AINTEN
 
__IO uint32_t APDMACTL
 
__IO uint32_t FDEN
 
__IO uint32_t FDCTL [6]
 
__IO uint32_t FDIEN
 
__IO uint32_t FDSTS
 
__IO uint32_t EADCPSCCTL
 
__IO uint32_t EADCPSC0
 
__IO uint32_t EADCPSC1
 
__IO uint32_t EADCPSCNT0
 
__IO uint32_t EADCPSCNT1
 
__IO uint32_t CAPINEN
 
__IO uint32_t CAPCTL
 
__I uint32_t CAPSTS
 
ECAPDAT_T CAPDAT [6]
 
__IO uint32_t PDMACTL
 
__I uint32_t PDMACAP [3]
 
__IO uint32_t CAPIEN
 
__IO uint32_t CAPIF
 
__I uint32_t PBUF [6]
 
__I uint32_t CMPBUF [6]
 
__I uint32_t CPSCBUF [3]
 
__I uint32_t FTCBUF [3]
 
__IO uint32_t FTCI
 

Detailed Description

Definition at line 71 of file epwm_reg.h.

Field Documentation

◆ AINTEN

EPWM_T::AINTEN

[0x0154] EPWM Accumulator Interrupt Enable Register

AINTEN

Offset: 0x154 EPWM Accumulator Interrupt Enable Register

BitsFieldDescriptions
[0]IFAIEN0
EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits
0 = Interrupt Flag accumulator interrupt Disabled.
1 = Interrupt Flag accumulator interrupt Enabled.
[1]IFAIEN1
EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits
0 = Interrupt Flag accumulator interrupt Disabled.
1 = Interrupt Flag accumulator interrupt Enabled.
[2]IFAIEN2
EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits
0 = Interrupt Flag accumulator interrupt Disabled.
1 = Interrupt Flag accumulator interrupt Enabled.
[3]IFAIEN3
EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits
0 = Interrupt Flag accumulator interrupt Disabled.
1 = Interrupt Flag accumulator interrupt Enabled.
[4]IFAIEN4
EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits
0 = Interrupt Flag accumulator interrupt Disabled.
1 = Interrupt Flag accumulator interrupt Enabled.
[5]IFAIEN5
EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits
0 = Interrupt Flag accumulator interrupt Disabled.
1 = Interrupt Flag accumulator interrupt Enabled.

Definition at line 4786 of file epwm_reg.h.

◆ AINTSTS

EPWM_T::AINTSTS

[0x0150] EPWM Accumulator Interrupt Flag Register

AINTSTS

Offset: 0x150 EPWM Accumulator Interrupt Flag Register

BitsFieldDescriptions
[0]IFAIF0
EPWM_CHn Interrupt Flag Accumulator Interrupt Flag
Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it.
[1]IFAIF1
EPWM_CHn Interrupt Flag Accumulator Interrupt Flag
Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it.
[2]IFAIF2
EPWM_CHn Interrupt Flag Accumulator Interrupt Flag
Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it.
[3]IFAIF3
EPWM_CHn Interrupt Flag Accumulator Interrupt Flag
Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it.
[4]IFAIF4
EPWM_CHn Interrupt Flag Accumulator Interrupt Flag
Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it.
[5]IFAIF5
EPWM_CHn Interrupt Flag Accumulator Interrupt Flag
Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it.

Definition at line 4785 of file epwm_reg.h.

◆ APDMACTL

EPWM_T::APDMACTL

[0x0158] EPWM Accumulator PDMA Control Register

APDMACTL

Offset: 0x158 EPWM Accumulator PDMA Control Register

BitsFieldDescriptions
[0]APDMAEN0
Channel N Accumulator PDMA Enable Bits
0 = Channel n PDMA function Disabled.
1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register.
[1]APDMAEN1
Channel N Accumulator PDMA Enable Bits
0 = Channel n PDMA function Disabled.
1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register.
[2]APDMAEN2
Channel N Accumulator PDMA Enable Bits
0 = Channel n PDMA function Disabled.
1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register.
[3]APDMAEN3
Channel N Accumulator PDMA Enable Bits
0 = Channel n PDMA function Disabled.
1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register.
[4]APDMAEN4
Channel N Accumulator PDMA Enable Bits
0 = Channel n PDMA function Disabled.
1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register.
[5]APDMAEN5
Channel N Accumulator PDMA Enable Bits
0 = Channel n PDMA function Disabled.
1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register.

Definition at line 4787 of file epwm_reg.h.

◆ BNF

EPWM_T::BNF

[0x00c0] EPWM Brake Noise Filter Register

BNF

Offset: 0xC0 EPWM Brake Noise Filter Register

BitsFieldDescriptions
[0]BRK0NFEN
EPWM Brake 0 Noise Filter Enable Bit
0 = Noise filter of EPWM Brake 0 Disabled.
1 = Noise filter of EPWM Brake 0 Enabled.
[3:1]BRK0NFSEL
Brake 0 Edge Detector Filter Clock Selection
000 = Filter clock = HCLK.
001 = Filter clock = HCLK/2.
010 = Filter clock = HCLK/4.
011 = Filter clock = HCLK/8.
100 = Filter clock = HCLK/16.
101 = Filter clock = HCLK/32.
110 = Filter clock = HCLK/64.
111 = Filter clock = HCLK/128.
[6:4]BRK0FCNT
Brake 0 Edge Detector Filter Count
The register bits control the Brake0 filter counter to count from 0 to BRK1FCNT.
[7]BRK0PINV
Brake 0 Pin Inverse
0 = The state of pin EPWMx_BRAKE0 is passed to the negative edge detector.
1 = The inversed state of pin EPWMx_BRAKE10 is passed to the negative edge detector.
[8]BRK1NFEN
EPWM Brake 1 Noise Filter Enable Bit
0 = Noise filter of EPWM Brake 1 Disabled.
1 = Noise filter of EPWM Brake 1 Enabled.
[11:9]BRK1NFSEL
Brake 1 Edge Detector Filter Clock Selection
000 = Filter clock = HCLK.
001 = Filter clock = HCLK/2.
010 = Filter clock = HCLK/4.
011 = Filter clock = HCLK/8.
100 = Filter clock = HCLK/16.
101 = Filter clock = HCLK/32.
110 = Filter clock = HCLK/64.
111 = Filter clock = HCLK/128.
[14:12]BRK1FCNT
Brake 1 Edge Detector Filter Count
The register bits control the Brake1 filter counter to count from 0 to BRK1FCNT.
[15]BRK1PINV
Brake 1 Pin Inverse
0 = The state of pin EPWMx_BRAKE1 is passed to the negative edge detector.
1 = The inversed state of pin EPWMx_BRAKE1 is passed to the negative edge detector.
[16]BK0SRC
Brake 0 Pin Source Select
For EPWM0 setting:
0 = Brake 0 pin source come from EPWM0_BRAKE0.
1 = Brake 0 pin source come from EPWM1_BRAKE0.
For EPWM1 setting:
0 = Brake 0 pin source come from EPWM1_BRAKE0.
1 = Brake 0 pin source come from EPWM0_BRAKE0.
[24]BK1SRC
Brake 1 Pin Source Select
For EPWM0 setting:
0 = Brake 1 pin source come from EPWM0_BRAKE1.
1 = Brake 1 pin source come from EPWM1_BRAKE1.
For EPWM1 setting:
0 = Brake 1 pin source come from EPWM1_BRAKE1.
1 = Brake 1 pin source come from EPWM0_BRAKE1.

Definition at line 4753 of file epwm_reg.h.

◆ BRKCTL

EPWM_T::BRKCTL[3]

[0x00c8] EPWM Brake Edge Detect Control Register 0/1,2/3,4/5

BRKCTL[3]

Offset: 0xC8 EPWM Brake Edge Detect Control Register 0/1,2/3,4/5

BitsFieldDescriptions
[0]CPO0EBEN
Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)
0 = ACMP0_O as edge-detect brake source Disabled.
1 = ACMP0_O as edge-detect brake source Enabled.
Note: This register is write protected. Refer toSYS_REGLCTL register.
[1]CPO1EBEN
Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)
0 = ACMP1_O as edge-detect brake source Disabled.
1 = ACMP1_O as edge-detect brake source Enabled.
Note: This register is write protected. Refer toSYS_REGLCTL register.
[4]BRKP0EEN
Enable EPWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect)
0 = EPWMx_BRAKE0 pin as edge-detect brake source Disabled.
1 = EPWMx_BRAKE0 pin as edge-detect brake source Enabled.
Note: This register is write protected. Refer toSYS_REGLCTL register.
[5]BRKP1EEN
Enable EPWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect)
0 = EPWMx_BRAKE1 pin as edge-detect brake source Disabled.
1 = EPWMx_BRAKE1 pin as edge-detect brake source Enabled.
Note: This register is write protected. Refer toSYS_REGLCTL register.
[7]SYSEBEN
Enable System Fail As Edge-detect Brake Source (Write Protect)
0 = System Fail condition as edge-detect brake source Disabled.
1 = System Fail condition as edge-detect brake source Enabled.
Note: This register is write protected. Refer toSYS_REGLCTL register.
[8]CPO0LBEN
Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)
0 = ACMP0_O as level-detect brake source Disabled.
1 = ACMP0_O as level-detect brake source Enabled.
Note: This register is write protected. Refer toSYS_REGLCTL register.
[9]CPO1LBEN
Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)
0 = ACMP1_O as level-detect brake source Disabled.
1 = ACMP1_O as level-detect brake source Enabled.
Note: This register is write protected. Refer toSYS_REGLCTL register.
[12]BRKP0LEN
Enable BKP0 Pin As Level-detect Brake Source (Write Protect)
0 = EPWMx_BRAKE0 pin as level-detect brake source Disabled.
1 = EPWMx_BRAKE0 pin as level-detect brake source Enabled.
Note: This register is write protected. Refer toSYS_REGLCTL register.
[13]BRKP1LEN
Enable BKP1 Pin As Level-detect Brake Source (Write Protect)
0 = EPWMx_BRAKE1 pin as level-detect brake source Disabled.
1 = EPWMx_BRAKE1 pin as level-detect brake source Enabled.
Note: This register is write protected. Refer toSYS_REGLCTL register.
[15]SYSLBEN
Enable System Fail As Level-detect Brake Source (Write Protect)
0 = System Fail condition as level-detect brake source Disabled.
1 = System Fail condition as level-detect brake source Enabled.
Note: This register is write protected. Refer toSYS_REGLCTL register.
[17:16]BRKAEVEN
EPWM Brake Action Select for Even Channel (Write Protect)
00 = EPWMx brake event will not affect even channels output.
01 = EPWM even channel output tri-state when EPWMx brake event happened.
10 = EPWM even channel output low level when EPWMx brake event happened.
11 = EPWM even channel output high level when EPWMx brake event happened.
Note: This register is write protected. Refer toSYS_REGLCTL register.
[19:18]BRKAODD
EPWM Brake Action Select for Odd Channel (Write Protect)
00 = EPWMx brake event will not affect odd channels output.
01 = EPWM odd channel output tri-state when EPWMx brake event happened.
10 = EPWM odd channel output low level when EPWMx brake event happened.
11 = EPWM odd channel output high level when EPWMx brake event happened.
Note: This register is write protected. Refer toSYS_REGLCTL register.
[20]EADCEBEN
Enable EADC Result Monitor (EADCRM) As Edge-detect Brake Source (Write Protect)
0 = EADCRM as edge-detect brake source Disabled.
1 = EADCRM as edge-detect brake source Enabled.
Note: This register is write protected. Refer toSYS_REGLCTL register.
[28]EADCLBEN
Enable EADC Result Monitor (EADCRM) As Level-detect Brake Source (Write Protect)
0 = EADCRM as level-detect brake source Disabled.
1 = EADCRM as level-detect brake source Enabled.
Note: This register is write protected. Refer toSYS_REGLCTL register.

Definition at line 4755 of file epwm_reg.h.

◆ CAPCTL

EPWM_T::CAPCTL

[0x0204] EPWM Capture Control Register

CAPCTL

Offset: 0x204 EPWM Capture Control Register

BitsFieldDescriptions
[0]CAPEN0
Capture Function Enable Bits
0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
1 = Capture function Enabled
Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
[1]CAPEN1
Capture Function Enable Bits
0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
1 = Capture function Enabled
Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
[2]CAPEN2
Capture Function Enable Bits
0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
1 = Capture function Enabled
Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
[3]CAPEN3
Capture Function Enable Bits
0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
1 = Capture function Enabled
Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
[4]CAPEN4
Capture Function Enable Bits
0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
1 = Capture function Enabled
Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
[5]CAPEN5
Capture Function Enable Bits
0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
1 = Capture function Enabled
Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
[8]CAPINV0
Capture Inverter Enable Bits
0 = Capture source inverter Disabled.
1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
[9]CAPINV1
Capture Inverter Enable Bits
0 = Capture source inverter Disabled.
1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
[10]CAPINV2
Capture Inverter Enable Bits
0 = Capture source inverter Disabled.
1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
[11]CAPINV3
Capture Inverter Enable Bits
0 = Capture source inverter Disabled.
1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
[12]CAPINV4
Capture Inverter Enable Bits
0 = Capture source inverter Disabled.
1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
[13]CAPINV5
Capture Inverter Enable Bits
0 = Capture source inverter Disabled.
1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
[16]RCRLDEN0
Rising Capture Reload Enable Bits
0 = Rising capture reload counter Disabled.
1 = Rising capture reload counter Enabled.
[17]RCRLDEN1
Rising Capture Reload Enable Bits
0 = Rising capture reload counter Disabled.
1 = Rising capture reload counter Enabled.
[18]RCRLDEN2
Rising Capture Reload Enable Bits
0 = Rising capture reload counter Disabled.
1 = Rising capture reload counter Enabled.
[19]RCRLDEN3
Rising Capture Reload Enable Bits
0 = Rising capture reload counter Disabled.
1 = Rising capture reload counter Enabled.
[20]RCRLDEN4
Rising Capture Reload Enable Bits
0 = Rising capture reload counter Disabled.
1 = Rising capture reload counter Enabled.
[21]RCRLDEN5
Rising Capture Reload Enable Bits
0 = Rising capture reload counter Disabled.
1 = Rising capture reload counter Enabled.
[24]FCRLDEN0
Falling Capture Reload Enable Bits
0 = Falling capture reload counter Disabled.
1 = Falling capture reload counter Enabled.
[25]FCRLDEN1
Falling Capture Reload Enable Bits
0 = Falling capture reload counter Disabled.
1 = Falling capture reload counter Enabled.
[26]FCRLDEN2
Falling Capture Reload Enable Bits
0 = Falling capture reload counter Disabled.
1 = Falling capture reload counter Enabled.
[27]FCRLDEN3
Falling Capture Reload Enable Bits
0 = Falling capture reload counter Disabled.
1 = Falling capture reload counter Enabled.
[28]FCRLDEN4
Falling Capture Reload Enable Bits
0 = Falling capture reload counter Disabled.
1 = Falling capture reload counter Enabled.
[29]FCRLDEN5
Falling Capture Reload Enable Bits
0 = Falling capture reload counter Disabled.
1 = Falling capture reload counter Enabled.

Definition at line 4804 of file epwm_reg.h.

◆ CAPDAT

ECAPDAT_T EPWM_T::CAPDAT[6]

[0x020C] EPWM Rising and Falling Capture Data Register 0~5

Definition at line 4806 of file epwm_reg.h.

◆ CAPIEN

EPWM_T::CAPIEN

[0x0250] EPWM Capture Interrupt Enable Register

CAPIEN

Offset: 0x250 EPWM Capture Interrupt Enable Register

BitsFieldDescriptions
[0]CAPRIEN0
EPWM Capture Rising Latch Interrupt Enable Bits
0 = Capture rising edge latch interrupt Disabled.
1 = Capture rising edge latch interrupt Enabled.
[1]CAPRIEN1
EPWM Capture Rising Latch Interrupt Enable Bits
0 = Capture rising edge latch interrupt Disabled.
1 = Capture rising edge latch interrupt Enabled.
[2]CAPRIEN2
EPWM Capture Rising Latch Interrupt Enable Bits
0 = Capture rising edge latch interrupt Disabled.
1 = Capture rising edge latch interrupt Enabled.
[3]CAPRIEN3
EPWM Capture Rising Latch Interrupt Enable Bits
0 = Capture rising edge latch interrupt Disabled.
1 = Capture rising edge latch interrupt Enabled.
[4]CAPRIEN4
EPWM Capture Rising Latch Interrupt Enable Bits
0 = Capture rising edge latch interrupt Disabled.
1 = Capture rising edge latch interrupt Enabled.
[5]CAPRIEN5
EPWM Capture Rising Latch Interrupt Enable Bits
0 = Capture rising edge latch interrupt Disabled.
1 = Capture rising edge latch interrupt Enabled.
[8]CAPFIEN0
EPWM Capture Falling Latch Interrupt Enable Bits
0 = Capture falling edge latch interrupt Disabled.
1 = Capture falling edge latch interrupt Enabled.
[9]CAPFIEN1
EPWM Capture Falling Latch Interrupt Enable Bits
0 = Capture falling edge latch interrupt Disabled.
1 = Capture falling edge latch interrupt Enabled.
[10]CAPFIEN2
EPWM Capture Falling Latch Interrupt Enable Bits
0 = Capture falling edge latch interrupt Disabled.
1 = Capture falling edge latch interrupt Enabled.
[11]CAPFIEN3
EPWM Capture Falling Latch Interrupt Enable Bits
0 = Capture falling edge latch interrupt Disabled.
1 = Capture falling edge latch interrupt Enabled.
[12]CAPFIEN4
EPWM Capture Falling Latch Interrupt Enable Bits
0 = Capture falling edge latch interrupt Disabled.
1 = Capture falling edge latch interrupt Enabled.
[13]CAPFIEN5
EPWM Capture Falling Latch Interrupt Enable Bits
0 = Capture falling edge latch interrupt Disabled.
1 = Capture falling edge latch interrupt Enabled.

Definition at line 4812 of file epwm_reg.h.

◆ CAPIF

EPWM_T::CAPIF

[0x0254] EPWM Capture Interrupt Flag Register

CAPIF

Offset: 0x254 EPWM Capture Interrupt Flag Register

BitsFieldDescriptions
[0]CRLIF0
EPWM Capture Rising Latch Interrupt Flag
This bit is writing 1 to clear.
0 = No capture rising latch condition happened.
1 = Capture rising latch condition happened, this flag will be set to high.
Note: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will cleared by hardware after PDMA transfer data.
[1]CRLIF1
EPWM Capture Rising Latch Interrupt Flag
This bit is writing 1 to clear.
0 = No capture rising latch condition happened.
1 = Capture rising latch condition happened, this flag will be set to high.
Note: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will cleared by hardware after PDMA transfer data.
[2]CRLIF2
EPWM Capture Rising Latch Interrupt Flag
This bit is writing 1 to clear.
0 = No capture rising latch condition happened.
1 = Capture rising latch condition happened, this flag will be set to high.
Note: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will cleared by hardware after PDMA transfer data.
[3]CRLIF3
EPWM Capture Rising Latch Interrupt Flag
This bit is writing 1 to clear.
0 = No capture rising latch condition happened.
1 = Capture rising latch condition happened, this flag will be set to high.
Note: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will cleared by hardware after PDMA transfer data.
[4]CRLIF4
EPWM Capture Rising Latch Interrupt Flag
This bit is writing 1 to clear.
0 = No capture rising latch condition happened.
1 = Capture rising latch condition happened, this flag will be set to high.
Note: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will cleared by hardware after PDMA transfer data.
[5]CRLIF5
EPWM Capture Rising Latch Interrupt Flag
This bit is writing 1 to clear.
0 = No capture rising latch condition happened.
1 = Capture rising latch condition happened, this flag will be set to high.
Note: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will cleared by hardware after PDMA transfer data.
[8]CFLIF0
EPWM Capture Falling Latch Interrupt Flag
This bit is writing 1 to clear.
0 = No capture falling latch condition happened.
1 = Capture falling latch condition happened, this flag will be set to high.
Note: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will cleared by hardware after PDMA transfer data.
[9]CFLIF1
EPWM Capture Falling Latch Interrupt Flag
This bit is writing 1 to clear.
0 = No capture falling latch condition happened.
1 = Capture falling latch condition happened, this flag will be set to high.
Note: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will cleared by hardware after PDMA transfer data.
[10]CFLIF2
EPWM Capture Falling Latch Interrupt Flag
This bit is writing 1 to clear.
0 = No capture falling latch condition happened.
1 = Capture falling latch condition happened, this flag will be set to high.
Note: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will cleared by hardware after PDMA transfer data.
[11]CFLIF3
EPWM Capture Falling Latch Interrupt Flag
This bit is writing 1 to clear.
0 = No capture falling latch condition happened.
1 = Capture falling latch condition happened, this flag will be set to high.
Note: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will cleared by hardware after PDMA transfer data.
[12]CFLIF4
EPWM Capture Falling Latch Interrupt Flag
This bit is writing 1 to clear.
0 = No capture falling latch condition happened.
1 = Capture falling latch condition happened, this flag will be set to high.
Note: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will cleared by hardware after PDMA transfer data.
[13]CFLIF5
EPWM Capture Falling Latch Interrupt Flag
This bit is writing 1 to clear.
0 = No capture falling latch condition happened.
1 = Capture falling latch condition happened, this flag will be set to high.
Note: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will cleared by hardware after PDMA transfer data.

Definition at line 4813 of file epwm_reg.h.

◆ CAPINEN

EPWM_T::CAPINEN

[0x0200] EPWM Capture Input Enable Register

CAPINEN

Offset: 0x200 EPWM Capture Input Enable Register

BitsFieldDescriptions
[0]CAPINEN0
Capture Input Enable Bits
0 = EPWM Channel capture input path Disabled
The input of EPWM channel capture function is always regarded as 0.
1 = EPWM Channel capture input path Enabled
The input of EPWM channel capture function comes from correlative multifunction pin.
[1]CAPINEN1
Capture Input Enable Bits
0 = EPWM Channel capture input path Disabled
The input of EPWM channel capture function is always regarded as 0.
1 = EPWM Channel capture input path Enabled
The input of EPWM channel capture function comes from correlative multifunction pin.
[2]CAPINEN2
Capture Input Enable Bits
0 = EPWM Channel capture input path Disabled
The input of EPWM channel capture function is always regarded as 0.
1 = EPWM Channel capture input path Enabled
The input of EPWM channel capture function comes from correlative multifunction pin.
[3]CAPINEN3
Capture Input Enable Bits
0 = EPWM Channel capture input path Disabled
The input of EPWM channel capture function is always regarded as 0.
1 = EPWM Channel capture input path Enabled
The input of EPWM channel capture function comes from correlative multifunction pin.
[4]CAPINEN4
Capture Input Enable Bits
0 = EPWM Channel capture input path Disabled
The input of EPWM channel capture function is always regarded as 0.
1 = EPWM Channel capture input path Enabled
The input of EPWM channel capture function comes from correlative multifunction pin.
[5]CAPINEN5
Capture Input Enable Bits
0 = EPWM Channel capture input path Disabled
The input of EPWM channel capture function is always regarded as 0.
1 = EPWM Channel capture input path Enabled
The input of EPWM channel capture function comes from correlative multifunction pin.

Definition at line 4803 of file epwm_reg.h.

◆ CAPSTS

EPWM_T::CAPSTS

[0x0208] EPWM Capture Status Register

CAPSTS

Offset: 0x208 EPWM Capture Status Register

BitsFieldDescriptions
[0]CRLIFOV0
Capture Rising Latch Interrupt Flag Overrun Status (Read Only)
This flag indicates if rising latch happened when the corresponding CRLIF is 1.
Note: This bit will be cleared automatically when user clear corresponding CRLIF.
[1]CRLIFOV1
Capture Rising Latch Interrupt Flag Overrun Status (Read Only)
This flag indicates if rising latch happened when the corresponding CRLIF is 1.
Note: This bit will be cleared automatically when user clear corresponding CRLIF.
[2]CRLIFOV2
Capture Rising Latch Interrupt Flag Overrun Status (Read Only)
This flag indicates if rising latch happened when the corresponding CRLIF is 1.
Note: This bit will be cleared automatically when user clear corresponding CRLIF.
[3]CRLIFOV3
Capture Rising Latch Interrupt Flag Overrun Status (Read Only)
This flag indicates if rising latch happened when the corresponding CRLIF is 1.
Note: This bit will be cleared automatically when user clear corresponding CRLIF.
[4]CRLIFOV4
Capture Rising Latch Interrupt Flag Overrun Status (Read Only)
This flag indicates if rising latch happened when the corresponding CRLIF is 1.
Note: This bit will be cleared automatically when user clear corresponding CRLIF.
[5]CRLIFOV5
Capture Rising Latch Interrupt Flag Overrun Status (Read Only)
This flag indicates if rising latch happened when the corresponding CRLIF is 1.
Note: This bit will be cleared automatically when user clear corresponding CRLIF.
[8]CFLIFOV0
Capture Falling Latch Interrupt Flag Overrun Status (Read Only)
This flag indicates if falling latch happened when the corresponding CFLIF is 1.
Note: This bit will be cleared automatically when user clear corresponding CFLIF.
[9]CFLIFOV1
Capture Falling Latch Interrupt Flag Overrun Status (Read Only)
This flag indicates if falling latch happened when the corresponding CFLIF is 1.
Note: This bit will be cleared automatically when user clear corresponding CFLIF.
[10]CFLIFOV2
Capture Falling Latch Interrupt Flag Overrun Status (Read Only)
This flag indicates if falling latch happened when the corresponding CFLIF is 1.
Note: This bit will be cleared automatically when user clear corresponding CFLIF.
[11]CFLIFOV3
Capture Falling Latch Interrupt Flag Overrun Status (Read Only)
This flag indicates if falling latch happened when the corresponding CFLIF is 1.
Note: This bit will be cleared automatically when user clear corresponding CFLIF.
[12]CFLIFOV4
Capture Falling Latch Interrupt Flag Overrun Status (Read Only)
This flag indicates if falling latch happened when the corresponding CFLIF is 1.
Note: This bit will be cleared automatically when user clear corresponding CFLIF.
[13]CFLIFOV5
Capture Falling Latch Interrupt Flag Overrun Status (Read Only)
This flag indicates if falling latch happened when the corresponding CFLIF is 1.
Note: This bit will be cleared automatically when user clear corresponding CFLIF.

Definition at line 4805 of file epwm_reg.h.

◆ CLKPSC

EPWM_T::CLKPSC[3]

[0x0014] EPWM Clock Prescale Register 0/1,2/3,4/5

CLKPSC[3]

Offset: 0x14 EPWM Clock Prescale Register 0/1, 2/3, 4/5

BitsFieldDescriptions
[11:0]CLKPSC
EPWM Counter Clock Prescale
The clock of EPWM counter is decided by clock prescaler
Each EPWM pair share one EPWM counter clock prescaler
The clock of EPWM counter is divided by (CLKPSC+ 1)

Definition at line 4722 of file epwm_reg.h.

◆ CLKSRC

EPWM_T::CLKSRC

[0x0010] EPWM Clock Source Register

CLKSRC

Offset: 0x10 EPWM Clock Source Register

BitsFieldDescriptions
[2:0]ECLKSRC0
EPWM_CH01 External Clock Source Select
000 = EPWMx_CLK, x denotes 0 or 1.
001 = TIMER0 overflow.
010 = TIMER1 overflow.
011 = TIMER2 overflow.
100 = TIMER3 overflow.
Others = Reserved.
[10:8]ECLKSRC2
EPWM_CH23 External Clock Source Select
000 = EPWMx_CLK, x denotes 0 or 1.
001 = TIMER0 overflow.
010 = TIMER1 overflow.
011 = TIMER2 overflow.
100 = TIMER3 overflow.
Others = Reserved.
[18:16]ECLKSRC4
EPWM_CH45 External Clock Source Select
000 = EPWMx_CLK, x denotes 0 or 1.
001 = TIMER0 overflow.
010 = TIMER1 overflow.
011 = TIMER2 overflow.
100 = TIMER3 overflow.
Others = Reserved.

Definition at line 4721 of file epwm_reg.h.

◆ CMPBUF

EPWM_T::CMPBUF[6]

[0x031c] EPWM CMPDAT0~5 Buffer

CMPBUF[6]

Offset: 0x31C EPWM CMPDAT0~5 Buffer

BitsFieldDescriptions
[15:0]CMPBUF
EPWM Comparator Register Buffer (Read Only)
Used as CMP active register.

Definition at line 4818 of file epwm_reg.h.

◆ CMPDAT

EPWM_T::CMPDAT[6]

[0x0050] EPWM Comparator Register 0~5

CMPDAT[6]

Offset: 0x50 EPWM Comparator Register 0

BitsFieldDescriptions
[15:0]CMP
EPWM Comparator Register
CMP use to compare with CNTR to generate EPWM waveform, interrupt and trigger EADC/DAC.
In independent mode, CMPDAT0~5 denote as 6 independent EPWM_CH0~5 compared point.
In complementary mode, CMPDAT0, 2, 4 denote as first compared point, and CMPDAT1, 3, 5 denote as second compared point for the corresponding 3 complementary pairs EPWM_CH0 and EPWM_CH1, EPWM_CH2 and EPWM_CH3, EPWM_CH4 and EPWM_CH5.

Definition at line 4733 of file epwm_reg.h.

◆ CNT

EPWM_T::CNT[6]

[0x0090] EPWM Counter Register 0~5

CNT[6]

Offset: 0x90 EPWM Counter Register 0~5

BitsFieldDescriptions
[15:0]CNT
EPWM Data Register (Read Only)
User can monitor CNTR to know the current value in 16-bit period counter.
[16]DIRF
EPWM Direction Indicator Flag (Read Only)
0 = Counter is Down count.
1 = Counter is UP count.

Definition at line 4745 of file epwm_reg.h.

◆ CNTCLR

EPWM_T::CNTCLR

[0x0024] EPWM Clear Counter Register

CNTCLR

Offset: 0x24 EPWM Clear Counter Register

BitsFieldDescriptions
[0]CNTCLR0
Clear EPWM Counter Control Bit
It is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n.
0 = No effect.
1 = Clear 16-bit EPWM counter to 0000H.
[1]CNTCLR1
Clear EPWM Counter Control Bit
It is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n.
0 = No effect.
1 = Clear 16-bit EPWM counter to 0000H.
[2]CNTCLR2
Clear EPWM Counter Control Bit
It is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n.
0 = No effect.
1 = Clear 16-bit EPWM counter to 0000H.
[3]CNTCLR3
Clear EPWM Counter Control Bit
It is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n.
0 = No effect.
1 = Clear 16-bit EPWM counter to 0000H.
[4]CNTCLR4
Clear EPWM Counter Control Bit
It is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n.
0 = No effect.
1 = Clear 16-bit EPWM counter to 0000H.
[5]CNTCLR5
Clear EPWM Counter Control Bit
It is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n.
0 = No effect.
1 = Clear 16-bit EPWM counter to 0000H.

Definition at line 4724 of file epwm_reg.h.

◆ CNTEN

EPWM_T::CNTEN

[0x0020] EPWM Counter Enable Register

CNTEN

Offset: 0x20 EPWM Counter Enable Register

BitsFieldDescriptions
[0]CNTEN0
EPWM Counter Enable Bits
0 = EPWM Counter and clock prescaler Stop Running.
1 = EPWM Counter and clock prescaler Start Running.
[1]CNTEN1
EPWM Counter Enable Bits
0 = EPWM Counter and clock prescaler Stop Running.
1 = EPWM Counter and clock prescaler Start Running.
[2]CNTEN2
EPWM Counter Enable Bits
0 = EPWM Counter and clock prescaler Stop Running.
1 = EPWM Counter and clock prescaler Start Running.
[3]CNTEN3
EPWM Counter Enable Bits
0 = EPWM Counter and clock prescaler Stop Running.
1 = EPWM Counter and clock prescaler Start Running.
[4]CNTEN4
EPWM Counter Enable Bits
0 = EPWM Counter and clock prescaler Stop Running.
1 = EPWM Counter and clock prescaler Start Running.
[5]CNTEN5
EPWM Counter Enable Bits
0 = EPWM Counter and clock prescaler Stop Running.
1 = EPWM Counter and clock prescaler Start Running.

Definition at line 4723 of file epwm_reg.h.

◆ CPSCBUF

EPWM_T::CPSCBUF[3]

[0x0334] EPWM CLKPSC0_1/2_3/4_5 Buffer

CPSCBUF[3]

Offset: 0x334 EPWM CLKPSC0_1/2_3/4_5 Buffer

BitsFieldDescriptions
[11:0]CPSCBUF
EPWM Counter Clock Prescale Buffer
Use as EPWM counter clock prescale active register.

Definition at line 4819 of file epwm_reg.h.

◆ CTL0

EPWM_T::CTL0

[0x0000] EPWM Control Register 0

CTL0

Offset: 0x00 EPWM Control Register 0

BitsFieldDescriptions
[0]CTRLD0
Center Re-load
In up-down counter type, PERIOD will load to PBUF at the end point of each period
CMPDAT will load to CMPBUF at the center point of a period
[1]CTRLD1
Center Re-load
In up-down counter type, PERIOD will load to PBUF at the end point of each period
CMPDAT will load to CMPBUF at the center point of a period
[2]CTRLD2
Center Re-load
In up-down counter type, PERIOD will load to PBUF at the end point of each period
CMPDAT will load to CMPBUF at the center point of a period
[3]CTRLD3
Center Re-load
In up-down counter type, PERIOD will load to PBUF at the end point of each period
CMPDAT will load to CMPBUF at the center point of a period
[4]CTRLD4
Center Re-load
In up-down counter type, PERIOD will load to PBUF at the end point of each period
CMPDAT will load to CMPBUF at the center point of a period
[5]CTRLD5
Center Re-load
In up-down counter type, PERIOD will load to PBUF at the end point of each period
CMPDAT will load to CMPBUF at the center point of a period
[8]WINLDEN0
Window Load Enable Bits
0 = PERIOD will load to PBUF at the end point of each period
CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
1 = PERIOD will load to PBUF at the end point of each period
CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set
The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success.
[9]WINLDEN1
Window Load Enable Bits
0 = PERIOD will load to PBUF at the end point of each period
CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
1 = PERIOD will load to PBUF at the end point of each period
CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set
The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success.
[10]WINLDEN2
Window Load Enable Bits
0 = PERIOD will load to PBUF at the end point of each period
CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
1 = PERIOD will load to PBUF at the end point of each period
CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set
The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success.
[11]WINLDEN3
Window Load Enable Bits
0 = PERIOD will load to PBUF at the end point of each period
CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
1 = PERIOD will load to PBUF at the end point of each period
CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set
The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success.
[12]WINLDEN4
Window Load Enable Bits
0 = PERIOD will load to PBUF at the end point of each period
CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
1 = PERIOD will load to PBUF at the end point of each period
CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set
The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success.
[13]WINLDEN5
Window Load Enable Bits
0 = PERIOD will load to PBUF at the end point of each period
CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
1 = PERIOD will load to PBUF at the end point of each period
CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set
The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success.
[16]IMMLDEN0
Immediately Load Enable Bits
0 = PERIOD will load to PBUF at the end point of each period
CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT.
Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid.
[17]IMMLDEN1
Immediately Load Enable Bits
0 = PERIOD will load to PBUF at the end point of each period
CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT.
Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid.
[18]IMMLDEN2
Immediately Load Enable Bits
0 = PERIOD will load to PBUF at the end point of each period
CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT.
Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid.
[19]IMMLDEN3
Immediately Load Enable Bits
0 = PERIOD will load to PBUF at the end point of each period
CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT.
Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid.
[20]IMMLDEN4
Immediately Load Enable Bits
0 = PERIOD will load to PBUF at the end point of each period
CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT.
Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid.
[21]IMMLDEN5
Immediately Load Enable Bits
0 = PERIOD will load to PBUF at the end point of each period
CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT.
Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid.
[24]GROUPEN
Group Function Enable Bit(S)
0 = The output waveform of each EPWM channel are independent.
1 = Unify the EPWM_CH2 and EPWM_CH4 to output the same waveform as EPWM_CH0 and unify the EPWM_CH3 and EPWM_CH5 to output the same waveform as EPWM_CH1.
[30]DBGHALT
ICE Debug Mode Counter Halt (Write Protect)
If counter halt is enabled, EPWM all counters will keep current value until exit ICE debug mode.
0 = ICE debug mode counter halt disable.
1 = ICE debug mode counter halt enable.
Note: This register is write protected. Refer toSYS_REGLCTL register.
[31]DBGTRIOFF
ICE Debug Mode Acknowledge Disable (Write Protect)
0 = ICE debug mode acknowledgement effects EPWM output.
EPWM pin will be forced as tri-state while ICE debug mode acknowledged.
1 = ICE debug mode acknowledgement disabled.
EPWM pin will keep output no matter ICE debug mode acknowledged or not.
Note: This register is write protected. Refer toSYS_REGLCTL register.

Definition at line 4717 of file epwm_reg.h.

◆ CTL1

EPWM_T::CTL1

[0x0004] EPWM Control Register 1

CTL1

Offset: 0x04 EPWM Control Register 1

BitsFieldDescriptions
[1:0]CNTTYPE0
EPWM Counter Behavior Type
00 = Up counter type (supports in capture mode).
01 = Down count type (supports in capture mode).
10 = Up-down counter type.
11 = Reserved.
[3:2]CNTTYPE1
EPWM Counter Behavior Type
00 = Up counter type (supports in capture mode).
01 = Down count type (supports in capture mode).
10 = Up-down counter type.
11 = Reserved.
[5:4]CNTTYPE2
EPWM Counter Behavior Type
00 = Up counter type (supports in capture mode).
01 = Down count type (supports in capture mode).
10 = Up-down counter type.
11 = Reserved.
[7:6]CNTTYPE3
EPWM Counter Behavior Type
00 = Up counter type (supports in capture mode).
01 = Down count type (supports in capture mode).
10 = Up-down counter type.
11 = Reserved.
[9:8]CNTTYPE4
EPWM Counter Behavior Type
00 = Up counter type (supports in capture mode).
01 = Down count type (supports in capture mode).
10 = Up-down counter type.
11 = Reserved.
[11:10]CNTTYPE5
EPWM Counter Behavior Type
00 = Up counter type (supports in capture mode).
01 = Down count type (supports in capture mode).
10 = Up-down counter type.
11 = Reserved.
[16]CNTMODE0
EPWM Counter Mode
0 = Auto-reload mode.
1 = One-shot mode.
[17]CNTMODE1
EPWM Counter Mode
0 = Auto-reload mode.
1 = One-shot mode.
[18]CNTMODE2
EPWM Counter Mode
0 = Auto-reload mode.
1 = One-shot mode.
[19]CNTMODE3
EPWM Counter Mode
0 = Auto-reload mode.
1 = One-shot mode.
[20]CNTMODE4
EPWM Counter Mode
0 = Auto-reload mode.
1 = One-shot mode.
[21]CNTMODE5
EPWM Counter Mode
0 = Auto-reload mode.
1 = One-shot mode.
[24]OUTMODE0
EPWM Output Mode
Each bit n controls the output mode of corresponding EPWM channel n.
0 = EPWM independent mode.
1 = EPWM complementary mode.
Note: When operating in group function, these bits must all set to the same mode.
[25]OUTMODE2
EPWM Output Mode
Each bit n controls the output mode of corresponding EPWM channel n.
0 = EPWM independent mode.
1 = EPWM complementary mode.
Note: When operating in group function, these bits must all set to the same mode.
[26]OUTMODE4
EPWM Output Mode
Each bit n controls the output mode of corresponding EPWM channel n.
0 = EPWM independent mode.
1 = EPWM complementary mode.
Note: When operating in group function, these bits must all set to the same mode.

Definition at line 4718 of file epwm_reg.h.

◆ DACTRGEN

EPWM_T::DACTRGEN

[0x00f4] EPWM Trigger DAC Enable Register

DACTRGEN

Offset: 0xF4 EPWM Trigger DAC Enable Register

BitsFieldDescriptions
[0]ZTE0
EPWM Zero Point Trigger DAC Enable Bits
EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1.
0 = EPWM period point trigger DAC function Disabled.
1 = EPWM period point trigger DAC function Enabled.
[1]ZTE1
EPWM Zero Point Trigger DAC Enable Bits
EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1.
0 = EPWM period point trigger DAC function Disabled.
1 = EPWM period point trigger DAC function Enabled.
[2]ZTE2
EPWM Zero Point Trigger DAC Enable Bits
EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1.
0 = EPWM period point trigger DAC function Disabled.
1 = EPWM period point trigger DAC function Enabled.
[3]ZTE3
EPWM Zero Point Trigger DAC Enable Bits
EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1.
0 = EPWM period point trigger DAC function Disabled.
1 = EPWM period point trigger DAC function Enabled.
[4]ZTE4
EPWM Zero Point Trigger DAC Enable Bits
EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1.
0 = EPWM period point trigger DAC function Disabled.
1 = EPWM period point trigger DAC function Enabled.
[5]ZTE5
EPWM Zero Point Trigger DAC Enable Bits
EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1.
0 = EPWM period point trigger DAC function Disabled.
1 = EPWM period point trigger DAC function Enabled.
[8]PTE0
EPWM Period Point Trigger DAC Enable Bits
EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1.
0 = EPWM period point trigger DAC function Disabled.
1 = EPWM period point trigger DAC function Enabled.
[9]PTE1
EPWM Period Point Trigger DAC Enable Bits
EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1.
0 = EPWM period point trigger DAC function Disabled.
1 = EPWM period point trigger DAC function Enabled.
[10]PTE2
EPWM Period Point Trigger DAC Enable Bits
EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1.
0 = EPWM period point trigger DAC function Disabled.
1 = EPWM period point trigger DAC function Enabled.
[11]PTE3
EPWM Period Point Trigger DAC Enable Bits
EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1.
0 = EPWM period point trigger DAC function Disabled.
1 = EPWM period point trigger DAC function Enabled.
[12]PTE4
EPWM Period Point Trigger DAC Enable Bits
EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1.
0 = EPWM period point trigger DAC function Disabled.
1 = EPWM period point trigger DAC function Enabled.
[13]PTE5
EPWM Period Point Trigger DAC Enable Bits
EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1.
0 = EPWM period point trigger DAC function Disabled.
1 = EPWM period point trigger DAC function Enabled.
[16]CUTRGE0
EPWM Compare Up Count Point Trigger DAC Enable Bits
EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1.
0 = EPWM Compare Up point trigger DAC function Disabled.
1 = EPWM Compare Up point trigger DAC function Enabled.
Note1: This bit should keep at 0 when EPWM counter operating in down counter type.
Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4.
[17]CUTRGE1
EPWM Compare Up Count Point Trigger DAC Enable Bits
EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1.
0 = EPWM Compare Up point trigger DAC function Disabled.
1 = EPWM Compare Up point trigger DAC function Enabled.
Note1: This bit should keep at 0 when EPWM counter operating in down counter type.
Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4.
[18]CUTRGE2
EPWM Compare Up Count Point Trigger DAC Enable Bits
EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1.
0 = EPWM Compare Up point trigger DAC function Disabled.
1 = EPWM Compare Up point trigger DAC function Enabled.
Note1: This bit should keep at 0 when EPWM counter operating in down counter type.
Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4.
[19]CUTRGE3
EPWM Compare Up Count Point Trigger DAC Enable Bits
EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1.
0 = EPWM Compare Up point trigger DAC function Disabled.
1 = EPWM Compare Up point trigger DAC function Enabled.
Note1: This bit should keep at 0 when EPWM counter operating in down counter type.
Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4.
[20]CUTRGE4
EPWM Compare Up Count Point Trigger DAC Enable Bits
EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1.
0 = EPWM Compare Up point trigger DAC function Disabled.
1 = EPWM Compare Up point trigger DAC function Enabled.
Note1: This bit should keep at 0 when EPWM counter operating in down counter type.
Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4.
[21]CUTRGE5
EPWM Compare Up Count Point Trigger DAC Enable Bits
EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1.
0 = EPWM Compare Up point trigger DAC function Disabled.
1 = EPWM Compare Up point trigger DAC function Enabled.
Note1: This bit should keep at 0 when EPWM counter operating in down counter type.
Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4.
[24]CDTRGE0
EPWM Compare Down Count Point Trigger DAC Enable Bits
EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1.
0 = EPWM Compare Down count point trigger DAC function Disabled.
1 = EPWM Compare Down count point trigger DAC function Enabled.
Note1: This bit should keep at 0 when EPWM counter operating in up counter type.
Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4.
[25]CDTRGE1
EPWM Compare Down Count Point Trigger DAC Enable Bits
EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1.
0 = EPWM Compare Down count point trigger DAC function Disabled.
1 = EPWM Compare Down count point trigger DAC function Enabled.
Note1: This bit should keep at 0 when EPWM counter operating in up counter type.
Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4.
[26]CDTRGE2
EPWM Compare Down Count Point Trigger DAC Enable Bits
EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1.
0 = EPWM Compare Down count point trigger DAC function Disabled.
1 = EPWM Compare Down count point trigger DAC function Enabled.
Note1: This bit should keep at 0 when EPWM counter operating in up counter type.
Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4.
[27]CDTRGE3
EPWM Compare Down Count Point Trigger DAC Enable Bits
EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1.
0 = EPWM Compare Down count point trigger DAC function Disabled.
1 = EPWM Compare Down count point trigger DAC function Enabled.
Note1: This bit should keep at 0 when EPWM counter operating in up counter type.
Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4.
[28]CDTRGE4
EPWM Compare Down Count Point Trigger DAC Enable Bits
EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1.
0 = EPWM Compare Down count point trigger DAC function Disabled.
1 = EPWM Compare Down count point trigger DAC function Enabled.
Note1: This bit should keep at 0 when EPWM counter operating in up counter type.
Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4.
[29]CDTRGE5
EPWM Compare Down Count Point Trigger DAC Enable Bits
EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1.
0 = EPWM Compare Down count point trigger DAC function Disabled.
1 = EPWM Compare Down count point trigger DAC function Enabled.
Note1: This bit should keep at 0 when EPWM counter operating in up counter type.
Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4.

Definition at line 4766 of file epwm_reg.h.

◆ DTCTL

EPWM_T::DTCTL[3]

[0x0070] EPWM Dead-Time Control Register 0/1,2/3,4/5

DTCTL[3]

Offset: 0x70 EPWM Dead-Time Control Register 0/1,2/3,4/5

BitsFieldDescriptions
[11:0]DTCNT
Dead-time Counter (Write Protect)
The dead-time can be calculated from the following formula:
Dead-time = (DTCNT[11:0]+1) * EPWM_CLK period.
Note: This register is write protected. Refer toSYS_REGLCTL register.
[16]DTEN
Enable Dead-time Insertion for EPWM Pair (EPWM_CH0, EPWM_CH1) (EPWM_CH2, EPWM_CH3) (EPWM_CH4, EPWM_CH5) (Write Protect)
Dead-time insertion is only active when this pair of complementary EPWM is enabled
If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay.
0 = Dead-time insertion Disabled on the pin pair.
1 = Dead-time insertion Enabled on the pin pair.
Note: This register is write protected. Refer toSYS_REGLCTL register.
[24]DTCKSEL
Dead-time Clock Select (Write Protect)
0 = Dead-time clock source from EPWM_CLK.
1 = Dead-time clock source from prescaler output.
Note: This register is write protected. Refer toREGWRPROT register.

Definition at line 4737 of file epwm_reg.h.

◆ EADCPSC0

__IO uint32_t EPWM_T::EADCPSC0

[0x0188] EPWM Trigger EADC Prescale Register 0

Definition at line 4796 of file epwm_reg.h.

◆ EADCPSC1

__IO uint32_t EPWM_T::EADCPSC1

[0x018C] EPWM Trigger EADC Prescale Register 1

Definition at line 4797 of file epwm_reg.h.

◆ EADCPSCCTL

__IO uint32_t EPWM_T::EADCPSCCTL

[0x0184] EPWM Trigger EADC Prescale Control Register

Definition at line 4795 of file epwm_reg.h.

◆ EADCPSCNT0

__IO uint32_t EPWM_T::EADCPSCNT0

[0x0190] EPWM Trigger EADC Prescale Counter Register 0

Definition at line 4798 of file epwm_reg.h.

◆ EADCPSCNT1

__IO uint32_t EPWM_T::EADCPSCNT1

[0x0194] EPWM Trigger EADC Prescale Counter Register 1

Definition at line 4799 of file epwm_reg.h.

◆ EADCTS0

EPWM_T::EADCTS0

[0x00f8] EPWM Trigger EADC Source Select Register 0

EADCTS0

Offset: 0xF8 EPWM Trigger EADC Source Select Register 0

BitsFieldDescriptions
[3:0]TRGSEL0
EPWM_CH0 Trigger EADC Source Select
0000 = EPWM_CH0 zero point.
0001 = EPWM_CH0 period point.
0010 = EPWM_CH0 zero or period point.
0011 = EPWM_CH0 up-count CMPDAT point.
0100 = EPWM_CH0 down-count CMPDAT point.
0101 = EPWM_CH1 zero point.
0110 = EPWM_CH1 period point.
0111 = EPWM_CH1 zero or period point.
1000 = EPWM_CH1 up-count CMPDAT point.
1001 = EPWM_CH1 down-count CMPDAT point.
1010 = EPWM_CH0 up-count free CMPDAT point.
1011 = EPWM_CH0 down-count free CMPDAT point.
1100 = EPWM_CH2 up-count free CMPDAT point.
1101 = EPWM_CH2 down-count free CMPDAT point.
1110 = EPWM_CH4 up-count free CMPDAT point.
1111 = EPWM_CH4 down-count free CMPDAT point.
[7]TRGEN0
EPWM_CH0 Trigger EADC enable bit
[11:8]TRGSEL1
EPWM_CH1 Trigger EADC Source Select
0000 = EPWM_CH0 zero point.
0001 = EPWM_CH0 period point.
0010 = EPWM_CH0 zero or period point.
0011 = EPWM_CH0 up-count CMPDAT point.
0100 = EPWM_CH0 down-count CMPDAT point.
0101 = EPWM_CH1 zero point.
0110 = EPWM_CH1 period point.
0111 = EPWM_CH1 zero or period point.
1000 = EPWM_CH1 up-count CMPDAT point.
1001 = EPWM_CH1 down-count CMPDAT point.
1010 = EPWM_CH0 up-count free CMPDAT point.
1011 = EPWM_CH0 down-count free CMPDAT point.
1100 = EPWM_CH2 up-count free CMPDAT point.
1101 = EPWM_CH2 down-count free CMPDAT point.
1110 = EPWM_CH4 up-count free CMPDAT point.
1111 = EPWM_CH4 down-count free CMPDAT point.
[15]TRGEN1
EPWM_CH1 Trigger EADC enable bit
[19:16]TRGSEL2
EPWM_CH2 Trigger EADC Source Select
0000 = EPWM_CH2 zero point.
0001 = EPWM_CH2 period point.
0010 = EPWM_CH2 zero or period point.
0011 = EPWM_CH2 up-count CMPDAT point.
0100 = EPWM_CH2 down-count CMPDAT point.
0101 = EPWM_CH3 zero point.
0110 = EPWM_CH3 period point.
0111 = EPWM_CH3 zero or period point.
1000 = EPWM_CH3 up-count CMPDAT point.
1001 = EPWM_CH3 down-count CMPDAT point.
1010 = EPWM_CH0 up-count free CMPDAT point.
1011 = EPWM_CH0 down-count free CMPDAT point.
1100 = EPWM_CH2 up-count free CMPDAT point.
1101 = EPWM_CH2 down-count free CMPDAT point.
1110 = EPWM_CH4 up-count free CMPDAT point.
1111 = EPWM_CH4 down-count free CMPDAT point.
[23]TRGEN2
EPWM_CH2 Trigger EADC enable bit
[27:24]TRGSEL3
EPWM_CH3 Trigger EADC Source Select
0000 = EPWM_CH2 zero point.
0001 = EPWM_CH2 period point.
0010 = EPWM_CH2 zero or period point.
0011 = EPWM_CH2 up-count CMPDAT point.
0100 = EPWM_CH2 down-count CMPDAT point.
0101 = EPWM_CH3 zero point.
0110 = EPWM_CH3 period point.
0111 = EPWM_CH3 zero or period point.
1000 = EPWM_CH3 up-count CMPDAT point.
1001 = EPWM_CH3 down-count CMPDAT point.
1010 = EPWM_CH0 up-count free CMPDAT point.
1011 = EPWM_CH0 down-count free CMPDAT point.
1100 = EPWM_CH2 up-count free CMPDAT point.
1101 = EPWM_CH2 down-count free CMPDAT point.
1110 = EPWM_CH4 up-count free CMPDAT point.
1111 = EPWM_CH4 down-count free CMPDAT point.
[31]TRGEN3
EPWM_CH3 Trigger EADC enable bit

Definition at line 4767 of file epwm_reg.h.

◆ EADCTS1

EPWM_T::EADCTS1

[0x00fc] EPWM Trigger EADC Source Select Register 1

EADCTS1

Offset: 0xFC EPWM Trigger EADC Source Select Register 1

BitsFieldDescriptions
[3:0]TRGSEL4
EPWM_CH4 Trigger EADC Source Select
0000 = EPWM_CH4 zero point.
0001 = EPWM_CH4 period point.
0010 = EPWM_CH4 zero or period point.
0011 = EPWM_CH4 up-count CMPDAT point.
0100 = EPWM_CH4 down-count CMPDAT point.
0101 = EPWM_CH5 zero point.
0110 = EPWM_CH5 period point.
0111 = EPWM_CH5 zero or period point.
1000 = EPWM_CH5 up-count CMPDAT point.
1001 = EPWM_CH5 down-count CMPDAT point.
1010 = EPWM_CH0 up-count free CMPDAT point.
1011 = EPWM_CH0 down-count free CMPDAT point.
1100 = EPWM_CH2 up-count free CMPDAT point.
1101 = EPWM_CH2 down-count free CMPDAT point.
1110 = EPWM_CH4 up-count free CMPDAT point.
1111 = EPWM_CH4 down-count free CMPDAT point.
[7]TRGEN4
EPWM_CH4 Trigger EADC enable bit
[11:8]TRGSEL5
EPWM_CH5 Trigger EADC Source Select
0000 = EPWM_CH4 zero point.
0001 = EPWM_CH4 period point.
0010 = EPWM_CH4 zero or period point.
0011 = EPWM_CH4 up-count CMPDAT point.
0100 = EPWM_CH4 down-count CMPDAT point.
0101 = EPWM_CH5 zero point.
0110 = EPWM_CH5 period point.
0111 = EPWM_CH5 zero or period point.
1000 = EPWM_CH5 up-count CMPDAT point.
1001 = EPWM_CH5 down-count CMPDAT point.
1010 = EPWM_CH0 up-count free CMPDAT point.
1011 = EPWM_CH0 down-count free CMPDAT point.
1100 = EPWM_CH2 up-count free CMPDAT point.
1101 = EPWM_CH2 down-count free CMPDAT point.
1110 = EPWM_CH4 up-count free CMPDAT point.
1111 = EPWM_CH4 down-count free CMPDAT point.
[15]TRGEN5
EPWM_CH5 Trigger EADC enable bit

Definition at line 4768 of file epwm_reg.h.

◆ FAILBRK

EPWM_T::FAILBRK

[0x00c4] EPWM System Fail Brake Control Register

FAILBRK

Offset: 0xC4 EPWM System Fail Brake Control Register

BitsFieldDescriptions
[0]CSSBRKEN
Clock Security System Detection Trigger EPWM Brake Function 0 Enable Bit
0 = Brake Function triggered by CSS detection Disabled.
1 = Brake Function triggered by CSS detection Enabled.
[1]BODBRKEN
Brown-out Detection Trigger EPWM Brake Function 0 Enable Bit
0 = Brake Function triggered by BOD Disabled.
1 = Brake Function triggered by BOD Enabled.
[2]RAMBRKEN
SRAM Parity Error Detection Trigger EPWM Brake Function 0 Enable Bit
0 = Brake Function triggered by SRAM parity error detection Disabled.
1 = Brake Function triggered by SRAM parity error detection Enabled.
[3]CORBRKEN
Core Lockup Detection Trigger EPWM Brake Function 0 Enable Bit
0 = Brake Function triggered by Core lockup detection Disabled.
1 = Brake Function triggered by Core lockup detection Enabled.

Definition at line 4754 of file epwm_reg.h.

◆ FDCTL

__IO uint32_t EPWM_T::FDCTL[6]

[0x0164~0x178] EPWM Fault Detect Control Register 0~5

Definition at line 4792 of file epwm_reg.h.

◆ FDEN

__IO uint32_t EPWM_T::FDEN

[0x0160] EPWM Fault Detect Enable Register

Definition at line 4791 of file epwm_reg.h.

◆ FDIEN

__IO uint32_t EPWM_T::FDIEN

[0x017C] EPWM Fault Detect Interrupt Enable Register

Definition at line 4793 of file epwm_reg.h.

◆ FDSTS

__IO uint32_t EPWM_T::FDSTS

[0x0180] EPWM Fault Detect Interrupt Flag Register

Definition at line 4794 of file epwm_reg.h.

◆ FTCBUF

EPWM_T::FTCBUF[3]

[0x0340] EPWM FTCMPDAT0_1/2_3/4_5 Buffer

FTCBUF[3]

Offset: 0x340 EPWM FTCMPDAT0_1/2_3/4_5 Buffer

BitsFieldDescriptions
[15:0]FTCMPBUF
EPWM FTCMPDAT Buffer (Read Only)
Used as FTCMPDAT active register.

Definition at line 4820 of file epwm_reg.h.

◆ FTCI

EPWM_T::FTCI

[0x034c] EPWM FTCMPDAT Indicator Register

FTCI

Offset: 0x34C EPWM FTCMPDAT Indicator Register

BitsFieldDescriptions
[0]FTCMU0
EPWM FTCMPDAT Up Indicator
Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=1, software can write 1 to clear this bit.
[1]FTCMU2
EPWM FTCMPDAT Up Indicator
Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=1, software can write 1 to clear this bit.
[2]FTCMU4
EPWM FTCMPDAT Up Indicator
Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=1, software can write 1 to clear this bit.
[8]FTCMD0
EPWM FTCMPDAT Down Indicator
Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=0, software can write 1 to clear this bit.
[9]FTCMD2
EPWM FTCMPDAT Down Indicator
Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=0, software can write 1 to clear this bit.
[10]FTCMD4
EPWM FTCMPDAT Down Indicator
Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=0, software can write 1 to clear this bit.

Definition at line 4821 of file epwm_reg.h.

◆ FTCMPDAT

EPWM_T::FTCMPDAT[3]

[0x0100] EPWM Free Trigger Compare Register 0/1,2/3,4/5

FTCMPDAT[3]

Offset: 0x100 EPWM Free Trigger Compare Register 0/1,2/3,4/5

BitsFieldDescriptions
[15:0]FTCMP
EPWM Free Trigger Compare Register
FTCMP use to compare with even CNTR to trigger EADC
FTCMPDAT0, 2, 4 corresponding complementary pairs EPWM_CH0 and EPWM_CH1, EPWM_CH2 and EPWM_CH3, EPWM_CH4 and EPWM_CH5.

Definition at line 4769 of file epwm_reg.h.

◆ IFA

EPWM_T::IFA[6]

[0x0130] EPWM Interrupt Flag Accumulator Register 0~5

IFA[6]

Offset: 0x130 EPWM Interrupt Flag Accumulator Register 0~5

BitsFieldDescriptions
[15:0]IFACNT
EPWM_CHn Interrupt Flag Counter
The register sets the count number which defines how many times of EPWM_CHn period occurs to set bit IFAIFn to request the EPWM period interrupt.
EPWM flag will be set in every IFACNT[15:0] times of EPWM period.
[24]STPMOD
EPWM_CHn Interrupt Flag Accumulator Stop Mode Enable Bits
0 = EPWM_CHn interrupt flag accumulator stop mode disable.
1 = EPWM_CHn interrupt flag accumulator stop mode enable.
[29:28]IFASEL
EPWM_CHn Interrupt Flag Accumulator Source Select
00 = CNT equal to Zero in channel n.
01 = CNT equal to PERIOD in channel n.
10 = CNT equal to CMPU in channel n.
11 = CNT equal to CMPD in channel n.
[31]IFAEN
EPWM_CHn Interrupt Flag Accumulator Enable Bits
0 = EPWM_CHn interrupt flag accumulator disable.
1 = EPWM_CHn interrupt flag accumulator enable.

Definition at line 4781 of file epwm_reg.h.

◆ INTEN0

EPWM_T::INTEN0

[0x00e0] EPWM Interrupt Enable Register 0

INTEN0

Offset: 0xE0 EPWM Interrupt Enable Register 0

BitsFieldDescriptions
[0]ZIEN0
EPWM Zero Point Interrupt Enable Bits
0 = Zero point interrupt Disabled.
1 = Zero point interrupt Enabled.
Note: Odd channels will read always 0 at complementary mode.
[1]ZIEN1
EPWM Zero Point Interrupt Enable Bits
0 = Zero point interrupt Disabled.
1 = Zero point interrupt Enabled.
Note: Odd channels will read always 0 at complementary mode.
[2]ZIEN2
EPWM Zero Point Interrupt Enable Bits
0 = Zero point interrupt Disabled.
1 = Zero point interrupt Enabled.
Note: Odd channels will read always 0 at complementary mode.
[3]ZIEN3
EPWM Zero Point Interrupt Enable Bits
0 = Zero point interrupt Disabled.
1 = Zero point interrupt Enabled.
Note: Odd channels will read always 0 at complementary mode.
[4]ZIEN4
EPWM Zero Point Interrupt Enable Bits
0 = Zero point interrupt Disabled.
1 = Zero point interrupt Enabled.
Note: Odd channels will read always 0 at complementary mode.
[5]ZIEN5
EPWM Zero Point Interrupt Enable Bits
0 = Zero point interrupt Disabled.
1 = Zero point interrupt Enabled.
Note: Odd channels will read always 0 at complementary mode.
[8]PIEN0
EPWM Period Point Interrupt Enable Bits
0 = Period point interrupt Disabled.
1 = Period point interrupt Enabled.
Note1: When up-down counter type period point means center point.
Note2: Odd channels will read always 0 at complementary mode.
[9]PIEN1
EPWM Period Point Interrupt Enable Bits
0 = Period point interrupt Disabled.
1 = Period point interrupt Enabled.
Note1: When up-down counter type period point means center point.
Note2: Odd channels will read always 0 at complementary mode.
[10]PIEN2
EPWM Period Point Interrupt Enable Bits
0 = Period point interrupt Disabled.
1 = Period point interrupt Enabled.
Note1: When up-down counter type period point means center point.
Note2: Odd channels will read always 0 at complementary mode.
[11]PIEN3
EPWM Period Point Interrupt Enable Bits
0 = Period point interrupt Disabled.
1 = Period point interrupt Enabled.
Note1: When up-down counter type period point means center point.
Note2: Odd channels will read always 0 at complementary mode.
[12]PIEN4
EPWM Period Point Interrupt Enable Bits
0 = Period point interrupt Disabled.
1 = Period point interrupt Enabled.
Note1: When up-down counter type period point means center point.
Note2: Odd channels will read always 0 at complementary mode.
[13]PIEN5
EPWM Period Point Interrupt Enable Bits
0 = Period point interrupt Disabled.
1 = Period point interrupt Enabled.
Note1: When up-down counter type period point means center point.
Note2: Odd channels will read always 0 at complementary mode.
[16]CMPUIEN0
EPWM Compare Up Count Interrupt Enable Bits
0 = Compare up count interrupt Disabled.
1 = Compare up count interrupt Enabled.
Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4.
[17]CMPUIEN1
EPWM Compare Up Count Interrupt Enable Bits
0 = Compare up count interrupt Disabled.
1 = Compare up count interrupt Enabled.
Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4.
[18]CMPUIEN2
EPWM Compare Up Count Interrupt Enable Bits
0 = Compare up count interrupt Disabled.
1 = Compare up count interrupt Enabled.
Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4.
[19]CMPUIEN3
EPWM Compare Up Count Interrupt Enable Bits
0 = Compare up count interrupt Disabled.
1 = Compare up count interrupt Enabled.
Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4.
[20]CMPUIEN4
EPWM Compare Up Count Interrupt Enable Bits
0 = Compare up count interrupt Disabled.
1 = Compare up count interrupt Enabled.
Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4.
[21]CMPUIEN5
EPWM Compare Up Count Interrupt Enable Bits
0 = Compare up count interrupt Disabled.
1 = Compare up count interrupt Enabled.
Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4.
[24]CMPDIEN0
EPWM Compare Down Count Interrupt Enable Bits
0 = Compare down count interrupt Disabled.
1 = Compare down count interrupt Enabled.
Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4.
[25]CMPDIEN1
EPWM Compare Down Count Interrupt Enable Bits
0 = Compare down count interrupt Disabled.
1 = Compare down count interrupt Enabled.
Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4.
[26]CMPDIEN2
EPWM Compare Down Count Interrupt Enable Bits
0 = Compare down count interrupt Disabled.
1 = Compare down count interrupt Enabled.
Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4.
[27]CMPDIEN3
EPWM Compare Down Count Interrupt Enable Bits
0 = Compare down count interrupt Disabled.
1 = Compare down count interrupt Enabled.
Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4.
[28]CMPDIEN4
EPWM Compare Down Count Interrupt Enable Bits
0 = Compare down count interrupt Disabled.
1 = Compare down count interrupt Enabled.
Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4.
[29]CMPDIEN5
EPWM Compare Down Count Interrupt Enable Bits
0 = Compare down count interrupt Disabled.
1 = Compare down count interrupt Enabled.
Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4.

Definition at line 4759 of file epwm_reg.h.

◆ INTEN1

EPWM_T::INTEN1

[0x00e4] EPWM Interrupt Enable Register 1

INTEN1

Offset: 0xE4 EPWM Interrupt Enable Register 1

BitsFieldDescriptions
[0]BRKEIEN0_1
EPWM Edge-detect Brake Interrupt Enable for Channel0/1 (Write Protect)
0 = Edge-detect Brake interrupt for channel0/1 Disabled.
1 = Edge-detect Brake interrupt for channel0/1 Enabled.
Note: This register is write protected. Refer toSYS_REGLCTL register.
[1]BRKEIEN2_3
EPWM Edge-detect Brake Interrupt Enable for Channel2/3 (Write Protect)
0 = Edge-detect Brake interrupt for channel2/3 Disabled.
1 = Edge-detect Brake interrupt for channel2/3 Enabled.
Note: This register is write protected. Refer toSYS_REGLCTL register.
[2]BRKEIEN4_5
EPWM Edge-detect Brake Interrupt Enable for Channel4/5 (Write Protect)
0 = Edge-detect Brake interrupt for channel4/5 Disabled.
1 = Edge-detect Brake interrupt for channel4/5 Enabled.
Note: This register is write protected. Refer toSYS_REGLCTL register.
[8]BRKLIEN0_1
EPWM Level-detect Brake Interrupt Enable for Channel0/1 (Write Protect)
0 = Level-detect Brake interrupt for channel0/1 Disabled.
1 = Level-detect Brake interrupt for channel0/1 Enabled.
Note: This register is write protected. Refer toSYS_REGLCTL register.
[9]BRKLIEN2_3
EPWM Level-detect Brake Interrupt Enable for Channel2/3 (Write Protect)
0 = Level-detect Brake interrupt for channel2/3 Disabled.
1 = Level-detect Brake interrupt for channel2/3 Enabled.
Note: This register is write protected. Refer toSYS_REGLCTL register.
[10]BRKLIEN4_5
EPWM Level-detect Brake Interrupt Enable for Channel4/5 (Write Protect)
0 = Level-detect Brake interrupt for channel4/5 Disabled.
1 = Level-detect Brake interrupt for channel4/5 Enabled.
Note: This register is write protected. Refer toSYS_REGLCTL register.

Definition at line 4760 of file epwm_reg.h.

◆ INTSTS0

EPWM_T::INTSTS0

[0x00e8] EPWM Interrupt Flag Register 0

INTSTS0

Offset: 0xE8 EPWM Interrupt Flag Register 0

BitsFieldDescriptions
[0]ZIF0
EPWM Zero Point Interrupt Flag
This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero.
[1]ZIF1
EPWM Zero Point Interrupt Flag
This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero.
[2]ZIF2
EPWM Zero Point Interrupt Flag
This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero.
[3]ZIF3
EPWM Zero Point Interrupt Flag
This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero.
[4]ZIF4
EPWM Zero Point Interrupt Flag
This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero.
[5]ZIF5
EPWM Zero Point Interrupt Flag
This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero.
[8]PIF0
EPWM Period Point Interrupt Flag
This bit is set by hardware when EPWM counter reaches EPWM_PERIODn, software can write 1 to clear this bit to zero.
[9]PIF1
EPWM Period Point Interrupt Flag
This bit is set by hardware when EPWM counter reaches EPWM_PERIODn, software can write 1 to clear this bit to zero.
[10]PIF2
EPWM Period Point Interrupt Flag
This bit is set by hardware when EPWM counter reaches EPWM_PERIODn, software can write 1 to clear this bit to zero.
[11]PIF3
EPWM Period Point Interrupt Flag
This bit is set by hardware when EPWM counter reaches EPWM_PERIODn, software can write 1 to clear this bit to zero.
[12]PIF4
EPWM Period Point Interrupt Flag
This bit is set by hardware when EPWM counter reaches EPWM_PERIODn, software can write 1 to clear this bit to zero.
[13]PIF5
EPWM Period Point Interrupt Flag
This bit is set by hardware when EPWM counter reaches EPWM_PERIODn, software can write 1 to clear this bit to zero.
[16]CMPUIF0
EPWM Compare Up Count Interrupt Flag
Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.
Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4.
[17]CMPUIF1
EPWM Compare Up Count Interrupt Flag
Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.
Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4.
[18]CMPUIF2
EPWM Compare Up Count Interrupt Flag
Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.
Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4.
[19]CMPUIF3
EPWM Compare Up Count Interrupt Flag
Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.
Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4.
[20]CMPUIF4
EPWM Compare Up Count Interrupt Flag
Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.
Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4.
[21]CMPUIF5
EPWM Compare Up Count Interrupt Flag
Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.
Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4.
[24]CMPDIF0
EPWM Compare Down Count Interrupt Flag
Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.
Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4.
[25]CMPDIF1
EPWM Compare Down Count Interrupt Flag
Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.
Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4.
[26]CMPDIF2
EPWM Compare Down Count Interrupt Flag
Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.
Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4.
[27]CMPDIF3
EPWM Compare Down Count Interrupt Flag
Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.
Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4.
[28]CMPDIF4
EPWM Compare Down Count Interrupt Flag
Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.
Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4.
[29]CMPDIF5
EPWM Compare Down Count Interrupt Flag
Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.
Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4.

Definition at line 4761 of file epwm_reg.h.

◆ INTSTS1

EPWM_T::INTSTS1

[0x00ec] EPWM Interrupt Flag Register 1

INTSTS1

Offset: 0xEC EPWM Interrupt Flag Register 1

BitsFieldDescriptions
[0]BRKEIF0
EPWM Channel0 Edge-detect Brake Interrupt Flag (Write Protect)
0 = EPWM channel0 edge-detect brake event do not happened.
1 = When EPWM channel0 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.
Note: This register is write protected. Refer toSYS_REGLCTL register.
[1]BRKEIF1
EPWM Channel1 Edge-detect Brake Interrupt Flag (Write Protect)
0 = EPWM channel1 edge-detect brake event do not happened.
1 = When EPWM channel1 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.
Note: This register is write protected. Refer toSYS_REGLCTL register.
[2]BRKEIF2
EPWM Channel2 Edge-detect Brake Interrupt Flag (Write Protect)
0 = EPWM channel2 edge-detect brake event do not happened.
1 = When EPWM channel2 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.
Note: This register is write protected. Refer toSYS_REGLCTL register.
[3]BRKEIF3
EPWM Channel3 Edge-detect Brake Interrupt Flag (Write Protect)
0 = EPWM channel3 edge-detect brake event do not happened.
1 = When EPWM channel3 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.
Note: This register is write protected. Refer toSYS_REGLCTL register.
[4]BRKEIF4
EPWM Channel4 Edge-detect Brake Interrupt Flag (Write Protect)
0 = EPWM channel4 edge-detect brake event do not happened.
1 = When EPWM channel4 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.
Note: This register is write protected. Refer toSYS_REGLCTL register.
[5]BRKEIF5
EPWM Channel5 Edge-detect Brake Interrupt Flag (Write Protect)
0 = EPWM channel5 edge-detect brake event do not happened.
1 = When EPWM channel5 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.
Note: This register is write protected. Refer toSYS_REGLCTL register.
[8]BRKLIF0
EPWM Channel0 Level-detect Brake Interrupt Flag (Write Protect)
0 = EPWM channel0 level-detect brake event do not happened.
1 = When EPWM channel0 level-detect brake event happened, this bit is set to 1, writing 1 to clear.
Note: This register is write protected. Refer toSYS_REGLCTL register.
[9]BRKLIF1
EPWM Channel1 Level-detect Brake Interrupt Flag (Write Protect)
0 = EPWM channel1 level-detect brake event do not happened.
1 = When EPWM channel1 level-detect brake event happened, this bit is set to 1, writing 1 to clear.
Note: This register is write protected. Refer toSYS_REGLCTL register.
[10]BRKLIF2
EPWM Channel2 Level-detect Brake Interrupt Flag (Write Protect)
0 = EPWM channel2 level-detect brake event do not happened.
1 = When EPWM channel2 level-detect brake event happened, this bit is set to 1, writing 1 to clear.
Note: This register is write protected. Refer toSYS_REGLCTL register.
[11]BRKLIF3
EPWM Channel3 Level-detect Brake Interrupt Flag (Write Protect)
0 = EPWM channel3 level-detect brake event do not happened.
1 = When EPWM channel3 level-detect brake event happened, this bit is set to 1, writing 1 to clear.
Note: This register is write protected. Refer toSYS_REGLCTL register.
[12]BRKLIF4
EPWM Channel4 Level-detect Brake Interrupt Flag (Write Protect)
0 = EPWM channel4 level-detect brake event do not happened.
1 = When EPWM channel4 level-detect brake event happened, this bit is set to 1, writing 1 to clear.
Note: This register is write protected. Refer toSYS_REGLCTL register.
[13]BRKLIF5
EPWM Channel5 Level-detect Brake Interrupt Flag (Write Protect)
0 = EPWM channel5 level-detect brake event do not happened.
1 = When EEPWM channel5 level-detect brake event happened, this bit is set to 1, writing 1 to clear.
Note: This register is write protected. Refer toSYS_REGLCTL register.
[16]BRKESTS0
EPWM Channel0 Edge-detect Brake Status (Read Only)
0 = EPWM channel0 edge-detect brake state is released.
1 = When EPWM channel0 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel0 at brake state, writing 1 to clear.
[17]BRKESTS1
EPWM Channel1 Edge-detect Brake Status (Read Only)
0 = EPWM channel1 edge-detect brake state is released.
1 = When EPWM channel1 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel1 at brake state, writing 1 to clear.
[18]BRKESTS2
EPWM Channel2 Edge-detect Brake Status (Read Only)
0 = EPWM channel2 edge-detect brake state is released.
1 = When EPWM channel2 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel2 at brake state, writing 1 to clear.
[19]BRKESTS3
EPWM Channel3 Edge-detect Brake Status (Read Only)
0 = EPWM channel3 edge-detect brake state is released.
1 = When EPWM channel3 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel3 at brake state, writing 1 to clear.
[20]BRKESTS4
EPWM Channel4 Edge-detect Brake Status (Read Only)
0 = EPWM channel4 edge-detect brake state is released.
1 = When EPWM channel4 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel4 at brake state, writing 1 to clear.
[21]BRKESTS5
EPWM Channel5 Edge-detect Brake Status (Read Only)
0 = EPWM channel5 edge-detect brake state is released.
1 = When EPWM channel5 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel5 at brake state, writing 1 to clear.
[24]BRKLSTS0
EPWM Channel0 Level-detect Brake Status (Read Only)
0 = EPWM channel0 level-detect brake state is released.
1 = When EPWM channel0 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel0 at brake state.
Note: This bit is read only and auto cleared by hardware
When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished
The EPWM waveform will start output from next full EPWM period.
[25]BRKLSTS1
EPWM Channel1 Level-detect Brake Status (Read Only)
0 = EPWM channel1 level-detect brake state is released.
1 = When EPWM channel1 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel1 at brake state.
Note: This bit is read only and auto cleared by hardware
When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished
The EPWM waveform will start output from next full EPWM period.
[26]BRKLSTS2
EPWM Channel2 Level-detect Brake Status (Read Only)
0 = EPWM channel2 level-detect brake state is released.
1 = When EPWM channel2 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel2 at brake state.
Note: This bit is read only and auto cleared by hardware
When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished
The EPWM waveform will start output from next full EPWM period.
[27]BRKLSTS3
EPWM Channel3 Level-detect Brake Status (Read Only)
0 = EPWM channel3 level-detect brake state is released.
1 = When EPWM channel3 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel3 at brake state.
Note: This bit is read only and auto cleared by hardware
When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished
The EPWM waveform will start output from next full EPWM period.
[28]BRKLSTS4
EPWM Channel4 Level-detect Brake Status (Read Only)
0 = EPWM channel4 level-detect brake state is released.
1 = When EPWM channel4 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel4 at brake state.
Note: This bit is read only and auto cleared by hardware
When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished
The EPWM waveform will start output from next full EPWM period.
[29]BRKLSTS5
EPWM Channel5 Level-detect Brake Status (Read Only)
0 = EPWM channel5 level-detect brake state is released.
1 = When EPWM channel5 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel5 at brake state.
Note: This bit is read only and auto cleared by hardware
When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished
The EPWM waveform will start output from next full EPWM period.

Definition at line 4762 of file epwm_reg.h.

◆ LEBCNT

EPWM_T::LEBCNT

[0x011c] EPWM Leading Edge Blanking Counter Register

LEBCNT

Offset: 0x11C EPWM Leading Edge Blanking Counter Register

BitsFieldDescriptions
[8:0]LEBCNT
EPWM Leading Edge Blanking Counter
This counter value decides leading edge blanking window size
Blanking window size = LEBCNT+1, and LEB counter clock base is ECLK.

Definition at line 4776 of file epwm_reg.h.

◆ LEBCTL

EPWM_T::LEBCTL

[0x0118] EPWM Leading Edge Blanking Control Register

LEBCTL

Offset: 0x118 EPWM Leading Edge Blanking Control Register

BitsFieldDescriptions
[0]LEBEN
EPWM Leading Edge Blanking Enable Bit
0 = EPWM Leading Edge Blanking Disabled.
1 = EPWM Leading Edge Blanking Enabled.
[8]SRCEN0
EPWM Leading Edge Blanking Source From EPWM_CH0 Enable Bit
0 = EPWM Leading Edge Blanking Source from EPWM_CH0 Disabled.
1 = EPWM Leading Edge Blanking Source from EPWM_CH0 Enabled.
[9]SRCEN2
EPWM Leading Edge Blanking Source From EPWM_CH2 Enable Bit
0 = EPWM Leading Edge Blanking Source from EPWM_CH2 Disabled.
1 = EPWM Leading Edge Blanking Source from EPWM_CH2 Enabled.
[10]SRCEN4
EPWM Leading Edge Blanking Source From EPWM_CH4 Enable Bit
0 = EPWM Leading Edge Blanking Source from EPWM_CH4 Disabled.
1 = EPWM Leading Edge Blanking Source from EPWM_CH4 Enabled.
[17:16]TRGTYPE
EPWM Leading Edge Blanking Trigger Type
0 = When detect leading edge blanking source rising edge, blanking counter start counting.
1 = When detect leading edge blanking source falling edge, blanking counter start counting.
2 = When detect leading edge blanking source rising or falling edge, blanking counter start counting.
3 = Reserved.

Definition at line 4775 of file epwm_reg.h.

◆ LOAD

EPWM_T::LOAD

[0x0028] EPWM Load Register

LOAD

Offset: 0x28 EPWM Load Register

BitsFieldDescriptions
[0]LOAD0
Re-load EPWM Comparator Register (CMPDAT) Control Bit
This bit is software write, hardware clear when current EPWM period end.
Write Operation:
0 = No effect.
1 = Set load window of window loading mode.
Read Operation:
0 = No load window is set.
1 = Load window is set.
Note: This bit only use in window loading mode, WINLDENn(EPWM_CTL0[13:8]) = 1.
[1]LOAD1
Re-load EPWM Comparator Register (CMPDAT) Control Bit
This bit is software write, hardware clear when current EPWM period end.
Write Operation:
0 = No effect.
1 = Set load window of window loading mode.
Read Operation:
0 = No load window is set.
1 = Load window is set.
Note: This bit only use in window loading mode, WINLDENn(EPWM_CTL0[13:8]) = 1.
[2]LOAD2
Re-load EPWM Comparator Register (CMPDAT) Control Bit
This bit is software write, hardware clear when current EPWM period end.
Write Operation:
0 = No effect.
1 = Set load window of window loading mode.
Read Operation:
0 = No load window is set.
1 = Load window is set.
Note: This bit only use in window loading mode, WINLDENn(EPWM_CTL0[13:8]) = 1.
[3]LOAD3
Re-load EPWM Comparator Register (CMPDAT) Control Bit
This bit is software write, hardware clear when current EPWM period end.
Write Operation:
0 = No effect.
1 = Set load window of window loading mode.
Read Operation:
0 = No load window is set.
1 = Load window is set.
Note: This bit only use in window loading mode, WINLDENn(EPWM_CTL0[13:8]) = 1.
[4]LOAD4
Re-load EPWM Comparator Register (CMPDAT) Control Bit
This bit is software write, hardware clear when current EPWM period end.
Write Operation:
0 = No effect.
1 = Set load window of window loading mode.
Read Operation:
0 = No load window is set.
1 = Load window is set.
Note: This bit only use in window loading mode, WINLDENn(EPWM_CTL0[13:8]) = 1.
[5]LOAD5
Re-load EPWM Comparator Register (CMPDAT) Control Bit
This bit is software write, hardware clear when current EPWM period end.
Write Operation:
0 = No effect.
1 = Set load window of window loading mode.
Read Operation:
0 = No load window is set.
1 = Load window is set.
Note: This bit only use in window loading mode, WINLDENn(EPWM_CTL0[13:8]) = 1.

Definition at line 4725 of file epwm_reg.h.

◆ MSK

EPWM_T::MSK

[0x00bc] EPWM Mask Data Register

MSK

Offset: 0xBC EPWM Mask Data Register

BitsFieldDescriptions
[0]MSKDAT0
EPWM Mask Data Bit
This data bit control the state of EPWMn output pin, if corresponding mask function is enabled.
0 = Output logic low to EPWM channel n.
1 = Output logic high to EPWM channel n.
[1]MSKDAT1
EPWM Mask Data Bit
This data bit control the state of EPWMn output pin, if corresponding mask function is enabled.
0 = Output logic low to EPWM channel n.
1 = Output logic high to EPWM channel n.
[2]MSKDAT2
EPWM Mask Data Bit
This data bit control the state of EPWMn output pin, if corresponding mask function is enabled.
0 = Output logic low to EPWM channel n.
1 = Output logic high to EPWM channel n.
[3]MSKDAT3
EPWM Mask Data Bit
This data bit control the state of EPWMn output pin, if corresponding mask function is enabled.
0 = Output logic low to EPWM channel n.
1 = Output logic high to EPWM channel n.
[4]MSKDAT4
EPWM Mask Data Bit
This data bit control the state of EPWMn output pin, if corresponding mask function is enabled.
0 = Output logic low to EPWM channel n.
1 = Output logic high to EPWM channel n.
[5]MSKDAT5
EPWM Mask Data Bit
This data bit control the state of EPWMn output pin, if corresponding mask function is enabled.
0 = Output logic low to EPWM channel n.
1 = Output logic high to EPWM channel n.

Definition at line 4752 of file epwm_reg.h.

◆ MSKEN

EPWM_T::MSKEN

[0x00b8] EPWM Mask Enable Register

MSKEN

Offset: 0xB8 EPWM Mask Enable Register

BitsFieldDescriptions
[0]MSKEN0
EPWM Mask Enable Bits
The EPWM output signal will be masked when this bit is enabled
The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data.
0 = EPWM output signal is non-masked.
1 = EPWM output signal is masked and output MSKDATn data.
[1]MSKEN1
EPWM Mask Enable Bits
The EPWM output signal will be masked when this bit is enabled
The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data.
0 = EPWM output signal is non-masked.
1 = EPWM output signal is masked and output MSKDATn data.
[2]MSKEN2
EPWM Mask Enable Bits
The EPWM output signal will be masked when this bit is enabled
The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data.
0 = EPWM output signal is non-masked.
1 = EPWM output signal is masked and output MSKDATn data.
[3]MSKEN3
EPWM Mask Enable Bits
The EPWM output signal will be masked when this bit is enabled
The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data.
0 = EPWM output signal is non-masked.
1 = EPWM output signal is masked and output MSKDATn data.
[4]MSKEN4
EPWM Mask Enable Bits
The EPWM output signal will be masked when this bit is enabled
The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data.
0 = EPWM output signal is non-masked.
1 = EPWM output signal is masked and output MSKDATn data.
[5]MSKEN5
EPWM Mask Enable Bits
The EPWM output signal will be masked when this bit is enabled
The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data.
0 = EPWM output signal is non-masked.
1 = EPWM output signal is masked and output MSKDATn data.

Definition at line 4751 of file epwm_reg.h.

◆ PBUF

EPWM_T::PBUF[6]

[0x0304] EPWM PERIOD0~5 Buffer

PBUF[6]

Offset: 0x304 EPWM PERIOD0~5 Buffer

BitsFieldDescriptions
[15:0]PBUF
EPWM Period Register Buffer (Read Only)
Used as PERIOD active register.

Definition at line 4817 of file epwm_reg.h.

◆ PDMACAP

EPWM_T::PDMACAP[3]

[0x0240] EPWM Capture Channel 01,23,45 PDMA Register

PDMACAP[3]

Offset: 0x240 EPWM Capture Channel 01 PDMA Register

BitsFieldDescriptions
[15:0]CAPBUF
EPWM Capture PDMA Register (Read Only)
This register is use as a buffer to transfer EPWM capture rising or falling data to memory by PDMA.

Definition at line 4808 of file epwm_reg.h.

◆ PDMACTL

EPWM_T::PDMACTL

[0x023c] EPWM PDMA Control Register

PDMACTL

Offset: 0x23C EPWM PDMA Control Register

BitsFieldDescriptions
[0]CHEN0_1
Channel 0/1 PDMA Enable
0 = Channel 0/1 PDMA function Disabled.
1 = Channel 0/1 PDMA function Enabled for the channel 0/1 captured data and transfer to memory.
[2:1]CAPMOD0_1
Select EPWM_RCAPDAT0/1 or EPWM_FCAPDAT0/1 to Do PDMA Transfer
00 = Reserved.
01 = EPWM_RCAPDAT0/1.
10 = EPWM_FCAPDAT0/1.
11 = Both EPWM_RCAPDAT0/1 and EPWM_FCAPDAT0/1.
[3]CAPORD0_1
Capture Channel 0/1 Rising/Falling Order
Set this bit to determine whether the EPWM_RCAPDAT0/1 or EPWM_FCAPDAT0/1 is the first captured data transferred to memory through PDMA when CAPMOD0_1 =11.
0 = EPWM_FCAPDAT0/1 is the first captured data to memory.
1 = EPWM_RCAPDAT0/1 is the first captured data to memory.
[4]CHSEL0_1
Select Channel 0/1 to Do PDMA Transfer
0 = Channel0.
1 = Channel1.
[8]CHEN2_3
Channel 2/3 PDMA Enable
0 = Channel 2/3 PDMA function Disabled.
1 = Channel 2/3 PDMA function Enabled for the channel 2/3 captured data and transfer to memory.
[10:9]CAPMOD2_3
Select EPWM_RCAPDAT2/3 or EPWM_FCAODAT2/3 to Do PDMA Transfer
00 = Reserved.
01 = EPWM_RCAPDAT2/3.
10 = EPWM_FCAPDAT2/3.
11 = Both EPWM_RCAPDAT2/3 and EPWM_FCAPDAT2/3.
[11]CAPORD2_3
Capture Channel 2/3 Rising/Falling Order
Set this bit to determine whether the EPWM_RCAPDAT2/3 or EPWM_FCAPDAT2/3 is the first captured data transferred to memory through PDMA when CAPMOD2_3 =11.
0 = EPWM_FCAPDAT2/3 is the first captured data to memory.
1 = EPWM_RCAPDAT2/3 is the first captured data to memory.
[12]CHSEL2_3
Select Channel 2/3 to Do PDMA Transfer
0 = Channel2.
1 = Channel3.
[16]CHEN4_5
Channel 4/5 PDMA Enable
0 = Channel 4/5 PDMA function Disabled.
1 = Channel 4/5 PDMA function Enabled for the channel 4/5 captured data and transfer to memory.
[18:17]CAPMOD4_5
Select EPWM_RCAPDAT4/5 or EPWM_FCAPDAT4/5 to Do PDMA Transfer
00 = Reserved.
01 = EPWM_RCAPDAT4/5.
10 = EPWM_FCAPDAT4/5.
11 = Both EPWM_RCAPDAT4/5 and EPWM_FCAPDAT4/5.
[19]CAPORD4_5
Capture Channel 4/5 Rising/Falling Order
Set this bit to determine whether the EPWM_RCAPDAT4/5 or EPWM_FCAPDAT4/5 is the first captured data transferred to memory through PDMA when CAPMOD4_5 =11.
0 = EPWM_FCAPDAT4/5 is the first captured data to memory.
1 = EPWM_RCAPDAT4/5 is the first captured data to memory.
[20]CHSEL4_5
Select Channel 4/5 to Do PDMA Transfer
0 = Channel4.
1 = Channel5.

Definition at line 4807 of file epwm_reg.h.

◆ PERIOD

EPWM_T::PERIOD[6]

[0x0030] EPWM Period Register 0~5

PERIOD[6]

Offset: 0x30 EPWM Period Register 0~5

BitsFieldDescriptions
[15:0]PERIOD
EPWM Period Register
Up-Count mode: In this mode, EPWM counter counts from 0 to PERIOD, and restarts from 0.
Down-Count mode: In this mode, EPWM counter counts from PERIOD to 0, and restarts from PERIOD.
EPWM period time = (PERIOD+1) * EPWM_CLK period.
Up-Down-Count mode: In this mode, EPWM counter counts from 0 to PERIOD, then decrements to 0 and repeats again.
EPWM period time = 2 * PERIOD * EPWM_CLK period.

Definition at line 4729 of file epwm_reg.h.

◆ PHS

EPWM_T::PHS[3]

[0x0080] EPWM Counter Phase Register 0/1,2/3,4/5

PHS[3]

Offset: 0x80 EPWM Counter Phase Register 0/1,2/3,4/5

BitsFieldDescriptions
[15:0]PHS
EPWM Synchronous Start Phase Bits
PHS determines the EPWM synchronous start phase value. These bits only use in synchronous function.

Definition at line 4741 of file epwm_reg.h.

◆ POEN

EPWM_T::POEN

[0x00d8] EPWM Output Enable Register

POEN

Offset: 0xD8 EPWM Output Enable Register

BitsFieldDescriptions
[0]POEN0
EPWM Pin Output Enable Bits
0 = EPWM pin at tri-state.
1 = EPWM pin in output mode.
[1]POEN1
EPWM Pin Output Enable Bits
0 = EPWM pin at tri-state.
1 = EPWM pin in output mode.
[2]POEN2
EPWM Pin Output Enable Bits
0 = EPWM pin at tri-state.
1 = EPWM pin in output mode.
[3]POEN3
EPWM Pin Output Enable Bits
0 = EPWM pin at tri-state.
1 = EPWM pin in output mode.
[4]POEN4
EPWM Pin Output Enable Bits
0 = EPWM pin at tri-state.
1 = EPWM pin in output mode.
[5]POEN5
EPWM Pin Output Enable Bits
0 = EPWM pin at tri-state.
1 = EPWM pin in output mode.

Definition at line 4757 of file epwm_reg.h.

◆ POLCTL

EPWM_T::POLCTL

[0x00d4] EPWM Pin Polar Inverse Register

POLCTL

Offset: 0xD4 EPWM Pin Polar Inverse Register

BitsFieldDescriptions
[0]PINV0
EPWM PIN Polar Inverse Control
The register controls polarity state of EPWM output.
0 = EPWM output polar inverse Disabled.
1 = EPWM output polar inverse Enabled.
[1]PINV1
EPWM PIN Polar Inverse Control
The register controls polarity state of EPWM output.
0 = EPWM output polar inverse Disabled.
1 = EPWM output polar inverse Enabled.
[2]PINV2
EPWM PIN Polar Inverse Control
The register controls polarity state of EPWM output.
0 = EPWM output polar inverse Disabled.
1 = EPWM output polar inverse Enabled.
[3]PINV3
EPWM PIN Polar Inverse Control
The register controls polarity state of EPWM output.
0 = EPWM output polar inverse Disabled.
1 = EPWM output polar inverse Enabled.
[4]PINV4
EPWM PIN Polar Inverse Control
The register controls polarity state of EPWM output.
0 = EPWM output polar inverse Disabled.
1 = EPWM output polar inverse Enabled.
[5]PINV5
EPWM PIN Polar Inverse Control
The register controls polarity state of EPWM output.
0 = EPWM output polar inverse Disabled.
1 = EPWM output polar inverse Enabled.

Definition at line 4756 of file epwm_reg.h.

◆ SSCTL

EPWM_T::SSCTL

[0x0110] EPWM Synchronous Start Control Register

SSCTL

Offset: 0x110 EPWM Synchronous Start Control Register

BitsFieldDescriptions
[0]SSEN0
EPWM Synchronous Start Function Enable Bits
When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN).
0 = EPWM synchronous start function Disabled.
1 = EPWM synchronous start function Enabled.
[1]SSEN1
EPWM Synchronous Start Function Enable Bits
When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN).
0 = EPWM synchronous start function Disabled.
1 = EPWM synchronous start function Enabled.
[2]SSEN2
EPWM Synchronous Start Function Enable Bits
When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN).
0 = EPWM synchronous start function Disabled.
1 = EPWM synchronous start function Enabled.
[3]SSEN3
EPWM Synchronous Start Function Enable Bits
When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN).
0 = EPWM synchronous start function Disabled.
1 = EPWM synchronous start function Enabled.
[4]SSEN4
EPWM Synchronous Start Function Enable Bits
When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN).
0 = EPWM synchronous start function Disabled.
1 = EPWM synchronous start function Enabled.
[5]SSEN5
EPWM Synchronous Start Function Enable Bits
When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN).
0 = EPWM synchronous start function Disabled.
1 = EPWM synchronous start function Enabled.
[9:8]SSRC
EPWM Synchronous Start Source Select Bits
00 = Synchronous start source come from EPWM0.
01 = Synchronous start source come from EPWM1.
10 = Synchronous start source come from BPWM0.
11 = Synchronous start source come from BPWM1.

Definition at line 4773 of file epwm_reg.h.

◆ SSTRG

EPWM_T::SSTRG

[0x0114] EPWM Synchronous Start Trigger Register

SSTRG

Offset: 0x114 EPWM Synchronous Start Trigger Register

BitsFieldDescriptions
[0]CNTSEN
EPWM Counter Synchronous Start Enable (Write Only)
PMW counter synchronous enable function is used to make selected EPWM channels (include EPWM0_CHx and EPWM1_CHx) start counting at the same time.
Writing this bit to 1 will also set the counter enable bit (CNTENn, n denotes channel 0 to 5) if correlated EPWM channel counter synchronous start function is enabled.

Definition at line 4774 of file epwm_reg.h.

◆ STATUS

EPWM_T::STATUS

[0x0120] EPWM Status Register

STATUS

Offset: 0x120 EPWM Status Register

BitsFieldDescriptions
[0]CNTMAXF0
Time-base Counter Equal to 0xFFFF Latched Flag
0 = indicates the time-base counter never reached its maximum value 0xFFFF.
1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit.
[1]CNTMAXF1
Time-base Counter Equal to 0xFFFF Latched Flag
0 = indicates the time-base counter never reached its maximum value 0xFFFF.
1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit.
[2]CNTMAXF2
Time-base Counter Equal to 0xFFFF Latched Flag
0 = indicates the time-base counter never reached its maximum value 0xFFFF.
1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit.
[3]CNTMAXF3
Time-base Counter Equal to 0xFFFF Latched Flag
0 = indicates the time-base counter never reached its maximum value 0xFFFF.
1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit.
[4]CNTMAXF4
Time-base Counter Equal to 0xFFFF Latched Flag
0 = indicates the time-base counter never reached its maximum value 0xFFFF.
1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit.
[5]CNTMAXF5
Time-base Counter Equal to 0xFFFF Latched Flag
0 = indicates the time-base counter never reached its maximum value 0xFFFF.
1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit.
[8]SYNCINF0
Input Synchronization Latched Flag
0 = Indicates no SYNC_IN event has occurred.
1 = Indicates an SYNC_IN event has occurred, software can write 1 to clear this bit.
[9]SYNCINF2
Input Synchronization Latched Flag
0 = Indicates no SYNC_IN event has occurred.
1 = Indicates an SYNC_IN event has occurred, software can write 1 to clear this bit.
[10]SYNCINF4
Input Synchronization Latched Flag
0 = Indicates no SYNC_IN event has occurred.
1 = Indicates an SYNC_IN event has occurred, software can write 1 to clear this bit.
[16]EADCTRGF0
EADC Start of Conversion Flag
0 = Indicates no EADC start of conversion trigger event has occurred.
1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
[17]EADCTRGF1
EADC Start of Conversion Flag
0 = Indicates no EADC start of conversion trigger event has occurred.
1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
[18]EADCTRGF2
EADC Start of Conversion Flag
0 = Indicates no EADC start of conversion trigger event has occurred.
1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
[19]EADCTRGF3
EADC Start of Conversion Flag
0 = Indicates no EADC start of conversion trigger event has occurred.
1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
[20]EADCTRGF4
EADC Start of Conversion Flag
0 = Indicates no EADC start of conversion trigger event has occurred.
1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
[21]EADCTRGF5
EADC Start of Conversion Flag
0 = Indicates no EADC start of conversion trigger event has occurred.
1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
[24]DACTRGF
DAC Start of Conversion Flag
0 = Indicates no DAC start of conversion trigger event has occurred.
1 = Indicates an DAC start of conversion trigger event has occurred, software can write 1 to clear this bit

Definition at line 4777 of file epwm_reg.h.

◆ SWBRK

EPWM_T::SWBRK

[0x00dc] EPWM Software Brake Control Register

SWBRK

Offset: 0xDC EPWM Software Brake Control Register

BitsFieldDescriptions
[0]BRKETRG0
EPWM Edge Brake Software Trigger (Write Only) (Write Protect)
Write 1 to this bit will trigger edge brake, and set BRKEIFn to 1 in EPWM_INTSTS1 register.
Note: This register is write protected. Refer toSYS_REGLCTL register.
[1]BRKETRG2
EPWM Edge Brake Software Trigger (Write Only) (Write Protect)
Write 1 to this bit will trigger edge brake, and set BRKEIFn to 1 in EPWM_INTSTS1 register.
Note: This register is write protected. Refer toSYS_REGLCTL register.
[2]BRKETRG4
EPWM Edge Brake Software Trigger (Write Only) (Write Protect)
Write 1 to this bit will trigger edge brake, and set BRKEIFn to 1 in EPWM_INTSTS1 register.
Note: This register is write protected. Refer toSYS_REGLCTL register.
[8]BRKLTRG0
EPWM Level Brake Software Trigger (Write Only) (Write Protect)
Write 1 to this bit will trigger level brake, and set BRKLIFn to 1 in EPWM_INTSTS1 register.
Note: This register is write protected. Refer toSYS_REGLCTL register.
[9]BRKLTRG2
EPWM Level Brake Software Trigger (Write Only) (Write Protect)
Write 1 to this bit will trigger level brake, and set BRKLIFn to 1 in EPWM_INTSTS1 register.
Note: This register is write protected. Refer toSYS_REGLCTL register.
[10]BRKLTRG4
EPWM Level Brake Software Trigger (Write Only) (Write Protect)
Write 1 to this bit will trigger level brake, and set BRKLIFn to 1 in EPWM_INTSTS1 register.
Note: This register is write protected. Refer toSYS_REGLCTL register.

Definition at line 4758 of file epwm_reg.h.

◆ SWSYNC

EPWM_T::SWSYNC

[0x000c] EPWM Software Control Synchronization Register

SWSYNC

Offset: 0x0C EPWM Software Control Synchronization Register

BitsFieldDescriptions
[0]SWSYNC0
Software SYNC Function
When SINSRCn (EPWM_SYNC[13:8]) is selected to 0, SYNC_OUT source is come from SYNC_IN or this bit.
[1]SWSYNC2
Software SYNC Function
When SINSRCn (EPWM_SYNC[13:8]) is selected to 0, SYNC_OUT source is come from SYNC_IN or this bit.
[2]SWSYNC4
Software SYNC Function
When SINSRCn (EPWM_SYNC[13:8]) is selected to 0, SYNC_OUT source is come from SYNC_IN or this bit.

Definition at line 4720 of file epwm_reg.h.

◆ SYNC

EPWM_T::SYNC

[0x0008] EPWM Synchronization Register

SYNC

Offset: 0x08 EPWM Synchronization Register

BitsFieldDescriptions
[0]PHSEN0
SYNC Phase Enable Bits
0 = EPWM counter disable to load PHS value.
1 = EPWM counter enable to load PHS value.
[1]PHSEN2
SYNC Phase Enable Bits
0 = EPWM counter disable to load PHS value.
1 = EPWM counter enable to load PHS value.
[2]PHSEN4
SYNC Phase Enable Bits
0 = EPWM counter disable to load PHS value.
1 = EPWM counter enable to load PHS value.
[9:8]SINSRC0
EPWM0_SYNC_IN Source Selection
00 = Synchronize source from SYNC_IN or SWSYNC.
01 = Counter equal to 0.
10 = Counter equal to EPWM_CMPDATm, m denotes 1, 3, 5.
11 = SYNC_OUT will not be generated.
[11:10]SINSRC2
EPWM0_SYNC_IN Source Selection
00 = Synchronize source from SYNC_IN or SWSYNC.
01 = Counter equal to 0.
10 = Counter equal to EPWM_CMPDATm, m denotes 1, 3, 5.
11 = SYNC_OUT will not be generated.
[13:12]SINSRC4
EPWM0_SYNC_IN Source Selection
00 = Synchronize source from SYNC_IN or SWSYNC.
01 = Counter equal to 0.
10 = Counter equal to EPWM_CMPDATm, m denotes 1, 3, 5.
11 = SYNC_OUT will not be generated.
[16]SNFLTEN
EPWM0_SYNC_IN Noise Filter Enable Bits
0 = Noise filter of input pin EPWM0_SYNC_IN is Disabled.
1 = Noise filter of input pin EPWM0_SYNC_IN is Enabled.
[19:17]SFLTCSEL
SYNC Edge Detector Filter Clock Selection
000 = Filter clock = HCLK.
001 = Filter clock = HCLK/2.
010 = Filter clock = HCLK/4.
011 = Filter clock = HCLK/8.
100 = Filter clock = HCLK/16.
101 = Filter clock = HCLK/32.
110 = Filter clock = HCLK/64.
111 = Filter clock = HCLK/128.
[22:20]SFLTCNT
SYNC Edge Detector Filter Count
The register bits control the counter number of edge detector.
[23]SINPINV
SYNC Input Pin Inverse
0 = The state of pin SYNC is passed to the negative edge detector.
1 = The inversed state of pin SYNC is passed to the negative edge detector.
[24]PHSDIR0
EPWM Phase Direction Control
0 = Control EPWM counter count decrement after synchronizing.
1 = Control EPWM counter count increment after synchronizing.
[25]PHSDIR2
EPWM Phase Direction Control
0 = Control EPWM counter count decrement after synchronizing.
1 = Control EPWM counter count increment after synchronizing.
[26]PHSDIR4
EPWM Phase Direction Control
0 = Control EPWM counter count decrement after synchronizing.
1 = Control EPWM counter count increment after synchronizing.

Definition at line 4719 of file epwm_reg.h.

◆ WGCTL0

EPWM_T::WGCTL0

[0x00b0] EPWM Generation Register 0

WGCTL0

Offset: 0xB0 EPWM Generation Register 0

BitsFieldDescriptions
[1:0]ZPCTL0
EPWM Zero Point Control
00 = Do nothing.
01 = EPWM zero point output Low.
10 = EPWM zero point output High.
11 = EPWM zero point output Toggle.
EPWM can control output level when EPWM counter count to zero.
[3:2]ZPCTL1
EPWM Zero Point Control
00 = Do nothing.
01 = EPWM zero point output Low.
10 = EPWM zero point output High.
11 = EPWM zero point output Toggle.
EPWM can control output level when EPWM counter count to zero.
[5:4]ZPCTL2
EPWM Zero Point Control
00 = Do nothing.
01 = EPWM zero point output Low.
10 = EPWM zero point output High.
11 = EPWM zero point output Toggle.
EPWM can control output level when EPWM counter count to zero.
[7:6]ZPCTL3
EPWM Zero Point Control
00 = Do nothing.
01 = EPWM zero point output Low.
10 = EPWM zero point output High.
11 = EPWM zero point output Toggle.
EPWM can control output level when EPWM counter count to zero.
[9:8]ZPCTL4
EPWM Zero Point Control
00 = Do nothing.
01 = EPWM zero point output Low.
10 = EPWM zero point output High.
11 = EPWM zero point output Toggle.
EPWM can control output level when EPWM counter count to zero.
[11:10]ZPCTL5
EPWM Zero Point Control
00 = Do nothing.
01 = EPWM zero point output Low.
10 = EPWM zero point output High.
11 = EPWM zero point output Toggle.
EPWM can control output level when EPWM counter count to zero.
[17:16]PRDPCTL0
EPWM Period (Center) Point Control
00 = Do nothing.
01 = EPWM period (center) point output Low.
10 = EPWM period (center) point output High.
11 = EPWM period (center) point output Toggle.
EPWM can control output level when EPWM counter count to (PERIODn+1).
Note: This bit is center point control when EPWM counter operating in up-down counter type.
[19:18]PRDPCTL1
EPWM Period (Center) Point Control
00 = Do nothing.
01 = EPWM period (center) point output Low.
10 = EPWM period (center) point output High.
11 = EPWM period (center) point output Toggle.
EPWM can control output level when EPWM counter count to (PERIODn+1).
Note: This bit is center point control when EPWM counter operating in up-down counter type.
[21:20]PRDPCTL2
EPWM Period (Center) Point Control
00 = Do nothing.
01 = EPWM period (center) point output Low.
10 = EPWM period (center) point output High.
11 = EPWM period (center) point output Toggle.
EPWM can control output level when EPWM counter count to (PERIODn+1).
Note: This bit is center point control when EPWM counter operating in up-down counter type.
[23:22]PRDPCTL3
EPWM Period (Center) Point Control
00 = Do nothing.
01 = EPWM period (center) point output Low.
10 = EPWM period (center) point output High.
11 = EPWM period (center) point output Toggle.
EPWM can control output level when EPWM counter count to (PERIODn+1).
Note: This bit is center point control when EPWM counter operating in up-down counter type.
[25:24]PRDPCTL4
EPWM Period (Center) Point Control
00 = Do nothing.
01 = EPWM period (center) point output Low.
10 = EPWM period (center) point output High.
11 = EPWM period (center) point output Toggle.
EPWM can control output level when EPWM counter count to (PERIODn+1).
Note: This bit is center point control when EPWM counter operating in up-down counter type.
[27:26]PRDPCTL5
EPWM Period (Center) Point Control
00 = Do nothing.
01 = EPWM period (center) point output Low.
10 = EPWM period (center) point output High.
11 = EPWM period (center) point output Toggle.
EPWM can control output level when EPWM counter count to (PERIODn+1).
Note: This bit is center point control when EPWM counter operating in up-down counter type.

Definition at line 4749 of file epwm_reg.h.

◆ WGCTL1

EPWM_T::WGCTL1

[0x00b4] EPWM Generation Register 1

WGCTL1

Offset: 0xB4 EPWM Generation Register 1

BitsFieldDescriptions
[1:0]CMPUCTL0
EPWM Compare Up Point Control
00 = Do nothing.
01 = EPWM compare up point output Low.
10 = EPWM compare up point output High.
11 = EPWM compare up point output Toggle.
EPWM can control output level when EPWM counter up count to CMPDAT.
Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4.
[3:2]CMPUCTL1
EPWM Compare Up Point Control
00 = Do nothing.
01 = EPWM compare up point output Low.
10 = EPWM compare up point output High.
11 = EPWM compare up point output Toggle.
EPWM can control output level when EPWM counter up count to CMPDAT.
Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4.
[5:4]CMPUCTL2
EPWM Compare Up Point Control
00 = Do nothing.
01 = EPWM compare up point output Low.
10 = EPWM compare up point output High.
11 = EPWM compare up point output Toggle.
EPWM can control output level when EPWM counter up count to CMPDAT.
Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4.
[7:6]CMPUCTL3
EPWM Compare Up Point Control
00 = Do nothing.
01 = EPWM compare up point output Low.
10 = EPWM compare up point output High.
11 = EPWM compare up point output Toggle.
EPWM can control output level when EPWM counter up count to CMPDAT.
Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4.
[9:8]CMPUCTL4
EPWM Compare Up Point Control
00 = Do nothing.
01 = EPWM compare up point output Low.
10 = EPWM compare up point output High.
11 = EPWM compare up point output Toggle.
EPWM can control output level when EPWM counter up count to CMPDAT.
Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4.
[11:10]CMPUCTL5
EPWM Compare Up Point Control
00 = Do nothing.
01 = EPWM compare up point output Low.
10 = EPWM compare up point output High.
11 = EPWM compare up point output Toggle.
EPWM can control output level when EPWM counter up count to CMPDAT.
Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4.
[17:16]CMPDCTL0
EPWM Compare Down Point Control
00 = Do nothing.
01 = EPWM compare down point output Low.
10 = EPWM compare down point output High.
11 = EPWM compare down point output Toggle.
EPWM can control output level when EPWM counter down count to CMPDAT.
Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4.
[19:18]CMPDCTL1
EPWM Compare Down Point Control
00 = Do nothing.
01 = EPWM compare down point output Low.
10 = EPWM compare down point output High.
11 = EPWM compare down point output Toggle.
EPWM can control output level when EPWM counter down count to CMPDAT.
Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4.
[21:20]CMPDCTL2
EPWM Compare Down Point Control
00 = Do nothing.
01 = EPWM compare down point output Low.
10 = EPWM compare down point output High.
11 = EPWM compare down point output Toggle.
EPWM can control output level when EPWM counter down count to CMPDAT.
Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4.
[23:22]CMPDCTL3
EPWM Compare Down Point Control
00 = Do nothing.
01 = EPWM compare down point output Low.
10 = EPWM compare down point output High.
11 = EPWM compare down point output Toggle.
EPWM can control output level when EPWM counter down count to CMPDAT.
Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4.
[25:24]CMPDCTL4
EPWM Compare Down Point Control
00 = Do nothing.
01 = EPWM compare down point output Low.
10 = EPWM compare down point output High.
11 = EPWM compare down point output Toggle.
EPWM can control output level when EPWM counter down count to CMPDAT.
Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4.
[27:26]CMPDCTL5
EPWM Compare Down Point Control
00 = Do nothing.
01 = EPWM compare down point output Low.
10 = EPWM compare down point output High.
11 = EPWM compare down point output Toggle.
EPWM can control output level when EPWM counter down count to CMPDAT.
Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4.

Definition at line 4750 of file epwm_reg.h.


The documentation for this struct was generated from the following file: