M480 BSP V3.05.006
The Board Support Package for M480 Series
clk.c
Go to the documentation of this file.
1/**************************************************************************/
10#include "NuMicro.h"
11
20int32_t g_CLK_i32ErrCode = 0;
33{
34 /* Disable CKO clock source */
36}
37
55void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En)
56{
57 /* CKO = clock source / 2^(u32ClkDiv + 1) */
58 CLK->CLKOCTL = CLK_CLKOCTL_CLKOEN_Msk | (u32ClkDiv) | (u32ClkDivBy1En << CLK_CLKOCTL_DIV1EN_Pos);
59
60 /* Enable CKO clock source */
62
63 /* Select CKO clock source */
64 CLK_SetModuleClock(CLKO_MODULE, u32ClkSrc, 0UL);
65}
66
74void CLK_PowerDown(void)
75{
76 uint32_t u32HIRCTRIMCTL;
77
78 /* Set the processor uses deep sleep as its low power mode */
79 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
80
81 /* Set system Power-down enabled */
82 CLK->PWRCTL |= (CLK_PWRCTL_PDEN_Msk);
83
84 /* Store HIRC control register */
85 u32HIRCTRIMCTL = SYS->IRCTCTL;
86
87 /* Disable HIRC auto trim */
88 SYS->IRCTCTL &= (~SYS_IRCTCTL_FREQSEL_Msk);
89
90 /* Chip enter Power-down mode after CPU run WFI instruction */
91 __WFI();
92
93 /* Restore HIRC control register */
94 SYS->IRCTCTL = u32HIRCTRIMCTL;
95}
96
104void CLK_Idle(void)
105{
106 /* Set the processor uses sleep as its low power mode */
107 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
108
109 /* Set chip in idle mode because of WFI command */
110 CLK->PWRCTL &= ~CLK_PWRCTL_PDEN_Msk;
111
112 /* Chip enter idle mode after CPU run WFI instruction */
113 __WFI();
114}
115
122uint32_t CLK_GetHXTFreq(void)
123{
124 uint32_t u32Freq;
125
127 {
128 u32Freq = __HXT;
129 }
130 else
131 {
132 u32Freq = 0UL;
133 }
134
135 return u32Freq;
136}
137
138
145uint32_t CLK_GetLXTFreq(void)
146{
147 uint32_t u32Freq;
149 {
150 u32Freq = __LXT;
151 }
152 else
153 {
154 u32Freq = 0UL;
155 }
156
157 return u32Freq;
158}
159
166uint32_t CLK_GetPCLK0Freq(void)
167{
168 uint32_t u32Freq;
170
172 {
173 u32Freq = SystemCoreClock;
174 }
176 {
177 u32Freq = SystemCoreClock / 2UL;
178 }
180 {
181 u32Freq = SystemCoreClock / 4UL;
182 }
184 {
185 u32Freq = SystemCoreClock / 8UL;
186 }
188 {
189 u32Freq = SystemCoreClock / 16UL;
190 }
191 else
192 {
193 u32Freq = SystemCoreClock;
194 }
195
196 return u32Freq;
197}
198
199
206uint32_t CLK_GetPCLK1Freq(void)
207{
208 uint32_t u32Freq;
210
212 {
213 u32Freq = SystemCoreClock;
214 }
216 {
217 u32Freq = SystemCoreClock / 2UL;
218 }
220 {
221 u32Freq = SystemCoreClock / 4UL;
222 }
224 {
225 u32Freq = SystemCoreClock / 8UL;
226 }
228 {
229 u32Freq = SystemCoreClock / 16UL;
230 }
231 else
232 {
233 u32Freq = SystemCoreClock;
234 }
235
236 return u32Freq;
237}
238
239
246uint32_t CLK_GetHCLKFreq(void)
247{
249 return SystemCoreClock;
250}
251
252
259uint32_t CLK_GetCPUFreq(void)
260{
262 return SystemCoreClock;
263}
264
265
273uint32_t CLK_SetCoreClock(uint32_t u32Hclk)
274{
275 uint32_t u32HIRCSTB;
276
277 /* Read HIRC clock source stable flag */
278 u32HIRCSTB = CLK->STATUS & CLK_STATUS_HIRCSTB_Msk;
279
280 /* The range of u32Hclk is running up to 192 MHz */
281 if(u32Hclk > FREQ_192MHZ)
282 {
283 u32Hclk = FREQ_192MHZ;
284 }
285
286 /* Switch HCLK clock source to HIRC clock for safe */
287 CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk;
289 CLK->CLKSEL0 |= CLK_CLKSEL0_HCLKSEL_Msk;
290 CLK->CLKDIV0 &= (~CLK_CLKDIV0_HCLKDIV_Msk);
291
292 /* Configure PLL setting if HXT clock is enabled */
294 {
295 u32Hclk = CLK_EnablePLL(CLK_PLLCTL_PLLSRC_HXT, u32Hclk);
296 }
297 /* Configure PLL setting if HXT clock is not enabled */
298 else
299 {
300 u32Hclk = CLK_EnablePLL(CLK_PLLCTL_PLLSRC_HIRC, u32Hclk);
301
302 /* Read HIRC clock source stable flag */
303 u32HIRCSTB = CLK->STATUS & CLK_STATUS_HIRCSTB_Msk;
304 }
305
306 /* Select HCLK clock source to PLL,
307 and update system core clock
308 */
310
311 /* Disable HIRC if HIRC is disabled before setting core clock */
312 if(u32HIRCSTB == 0UL)
313 {
314 CLK->PWRCTL &= ~CLK_PWRCTL_HIRCEN_Msk;
315 }
316
317 /* Return actually HCLK frequency is PLL frequency divide 1 */
318 return u32Hclk;
319}
320
335void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv)
336{
337 uint32_t u32HIRCSTB;
338
339 /* Read HIRC clock source stable flag */
340 u32HIRCSTB = CLK->STATUS & CLK_STATUS_HIRCSTB_Msk;
341
342 /* Switch to HIRC for Safe. Avoid HCLK too high when applying new divider. */
343 CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk;
345 CLK->CLKSEL0 = (CLK->CLKSEL0 & (~CLK_CLKSEL0_HCLKSEL_Msk)) | CLK_CLKSEL0_HCLKSEL_HIRC;
346
347 /* Apply new Divider */
348 CLK->CLKDIV0 = (CLK->CLKDIV0 & (~CLK_CLKDIV0_HCLKDIV_Msk)) | u32ClkDiv;
349
350 /* Switch HCLK to new HCLK source */
351 CLK->CLKSEL0 = (CLK->CLKSEL0 & (~CLK_CLKSEL0_HCLKSEL_Msk)) | u32ClkSrc;
352
353 /* Update System Core Clock */
355
356 /* Disable HIRC if HIRC is disabled before switching HCLK source */
357 if(u32HIRCSTB == 0UL)
358 {
359 CLK->PWRCTL &= ~CLK_PWRCTL_HIRCEN_Msk;
360 }
361}
362
505void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv)
506{
507 uint32_t u32sel = 0U, u32div = 0U;
508
509 if(MODULE_CLKDIV_Msk(u32ModuleIdx) != MODULE_NoMsk)
510 {
511 /* Get clock divider control register address */
512 if ((SYS->CSERVER & SYS_CSERVER_VERSION_Msk) == 0x1) // M480LD
513 {
514 if(MODULE_CLKDIV(u32ModuleIdx) == 2U && MODULE_IP_EN_Pos_ENC(u32ModuleIdx) == 31U) //EADC1
515 {
516 u32div = (uint32_t)&CLK->CLKDIV2;
517 }
518 else if(MODULE_CLKDIV(u32ModuleIdx) == 2U && MODULE_IP_EN_Pos_ENC(u32ModuleIdx) == 29U) //I2S0
519 {
520 u32div = (uint32_t)&CLK->CLKDIV2;
521 }
522 else if (MODULE_CLKDIV(u32ModuleIdx) == 2U)
523 {
524 u32div = (uint32_t)&CLK->CLKDIV3;
525 }
526 else if (MODULE_CLKDIV(u32ModuleIdx) == 3U)
527 {
528 u32div = (uint32_t)&CLK->CLKDIV4;
529 }
530 else
531 {
532 u32div = (uint32_t)&CLK->CLKDIV0 + ((MODULE_CLKDIV(u32ModuleIdx)) * 4U);
533 }
534 }
535 else
536 {
537 /* Get clock divider control register address */
538 if(MODULE_CLKDIV(u32ModuleIdx) == 2U)
539 {
540 u32div = (uint32_t)&CLK->CLKDIV3;
541 }
542 else if (MODULE_CLKDIV(u32ModuleIdx) == 3U)
543 {
544 u32div = (uint32_t)&CLK->CLKDIV4;
545 }
546 else
547 {
548 u32div = (uint32_t)&CLK->CLKDIV0 + ((MODULE_CLKDIV(u32ModuleIdx)) * 4U);
549 }
550 }
551
552 /* Apply new divider */
553 M32(u32div) = (M32(u32div) & (~(MODULE_CLKDIV_Msk(u32ModuleIdx) << MODULE_CLKDIV_Pos(u32ModuleIdx)))) | u32ClkDiv;
554 }
555
556 if(MODULE_CLKSEL_Msk(u32ModuleIdx) != MODULE_NoMsk)
557 {
558 /* Get clock select control register address */
559 u32sel = (uint32_t)&CLK->CLKSEL0 + ((MODULE_CLKSEL(u32ModuleIdx)) * 4U);
560 /* Set new clock selection setting */
561 M32(u32sel) = (M32(u32sel) & (~(MODULE_CLKSEL_Msk(u32ModuleIdx) << MODULE_CLKSEL_Pos(u32ModuleIdx)))) | u32ClkSrc;
562 }
563}
564
577void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc)
578{
579 CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_STCLKSEL_Msk) | u32ClkSrc;
580
581}
582
594void CLK_EnableXtalRC(uint32_t u32ClkMask)
595{
596 CLK->PWRCTL |= u32ClkMask;
597}
598
610void CLK_DisableXtalRC(uint32_t u32ClkMask)
611{
612 CLK->PWRCTL &= ~u32ClkMask;
613}
614
687void CLK_EnableModuleClock(uint32_t u32ModuleIdx)
688{
689 uint32_t u32tmpVal = 0UL, u32tmpAddr = 0UL;
690
691 u32tmpVal = (1UL << MODULE_IP_EN_Pos(u32ModuleIdx));
692 u32tmpAddr = (uint32_t)&CLK->AHBCLK;
693 u32tmpAddr += ((MODULE_APBCLK(u32ModuleIdx) * 4UL));
694
695 *(volatile uint32_t *)u32tmpAddr |= u32tmpVal;
696}
697
770void CLK_DisableModuleClock(uint32_t u32ModuleIdx)
771{
772 uint32_t u32tmpVal = 0UL, u32tmpAddr = 0UL;
773
774 u32tmpVal = ~(1UL << MODULE_IP_EN_Pos(u32ModuleIdx));
775 u32tmpAddr = (uint32_t)&CLK->AHBCLK;
776 u32tmpAddr += ((MODULE_APBCLK(u32ModuleIdx) * 4UL));
777
778 *(uint32_t *)u32tmpAddr &= u32tmpVal;
779}
780
781
792uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq)
793{
794 uint32_t u32PllSrcClk, u32NR, u32NF, u32NO, u32CLK_SRC, u32PllClk;
795 uint32_t u32Tmp, u32Tmp2, u32Tmp3, u32Min, u32MinNF, u32MinNR, u32MinNO, u32basFreq;
796
797 /* Disable PLL first to avoid unstable when setting PLL */
799
800 /* PLL source clock is from HXT */
801 if(u32PllClkSrc == CLK_PLLCTL_PLLSRC_HXT)
802 {
803 /* Enable HXT clock */
804 CLK->PWRCTL |= CLK_PWRCTL_HXTEN_Msk;
805
806 /* Wait for HXT clock ready */
808
809 /* Select PLL source clock from HXT */
810 u32CLK_SRC = CLK_PLLCTL_PLLSRC_HXT;
811 u32PllSrcClk = __HXT;
812
813 /* Check HXT range. Set u32NR start value */
814 /* Constraint 1: 4MHz <= FREF <= 8MHz */
815 if((u32PllSrcClk >= 4000000UL) && (u32PllSrcClk <= 8000000UL))
816 u32NR = 1UL;
817 else
818 u32NR = 2UL;
819 }
820
821 /* PLL source clock is from HIRC */
822 else
823 {
824 /* Enable HIRC clock */
825 CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk;
826
827 /* Wait for HIRC clock ready */
829
830 /* Select PLL source clock from HIRC */
831 u32CLK_SRC = CLK_PLLCTL_PLLSRC_HIRC;
832 u32PllSrcClk = __HIRC;
833
834 /* u32NR start from 4 when FIN = 22.1184MHz to avoid calculation overflow */
835 u32NR = 4UL;
836 }
837
838 if((u32PllFreq <= FREQ_500MHZ) && (u32PllFreq >= FREQ_50MHZ))
839 {
840
841 /* Find best solution */
842 u32Min = (uint32_t) - 1;
843 u32MinNR = 0UL;
844 u32MinNF = 0UL;
845 u32MinNO = 0UL;
846 u32basFreq = u32PllFreq;
847
848 for(u32NO = 1UL; u32NO <= 4UL; u32NO++)
849 {
850 /* Break when get good results */
851 if (u32Min == 0UL)
852 {
853 break;
854 }
855
856 if (u32NO != 3UL)
857 {
858
859 if(u32NO == 4UL)
860 {
861 u32PllFreq = u32basFreq << 2;
862 }
863 else if(u32NO == 2UL)
864 {
865 u32PllFreq = u32basFreq << 1;
866 }
867 else
868 {
869 }
870
871 for(u32NR = 1UL; u32NR <= 32UL; u32NR++)
872 {
873 /* Break when get good results */
874 if (u32Min == 0UL)
875 {
876 break;
877 }
878
879 u32Tmp = u32PllSrcClk / u32NR;
880 if((u32Tmp >= 4000000UL) && (u32Tmp <= 8000000UL))
881 {
882 for(u32NF = 2UL; u32NF <= 513UL; u32NF++)
883 {
884 /* u32Tmp2 is shifted 2 bits to avoid overflow */
885 u32Tmp2 = (((u32Tmp * 2UL) >> 2) * u32NF);
886
887 if((u32Tmp2 >= FREQ_50MHZ) && (u32Tmp2 <= FREQ_125MHZ))
888 {
889 u32Tmp3 = (u32Tmp2 > (u32PllFreq>>2)) ? u32Tmp2 - (u32PllFreq>>2) : (u32PllFreq>>2) - u32Tmp2;
890 if(u32Tmp3 < u32Min)
891 {
892 u32Min = u32Tmp3;
893 u32MinNR = u32NR;
894 u32MinNF = u32NF;
895 u32MinNO = u32NO;
896
897 /* Break when get good results */
898 if(u32Min == 0UL)
899 {
900 break;
901 }
902 }
903 }
904 }
905 }
906 }
907 }
908 }
909
910 /* Enable and apply new PLL setting. */
911 CLK->PLLCTL = u32CLK_SRC | ((u32MinNO - 1UL) << 14) | ((u32MinNR - 1UL) << 9) | (u32MinNF - 2UL);
912
913 /* Wait for PLL clock stable */
915
916 /* Actual PLL output clock frequency */
917 u32PllClk = u32PllSrcClk / (u32MinNO * (u32MinNR)) * (u32MinNF) * 2UL;
918 }
919 else
920 {
921 /* Wrong frequency request. Just return default setting. */
922 /* Apply default PLL setting and return */
923 if(u32PllClkSrc == CLK_PLLCTL_PLLSRC_HXT)
924 {
925 CLK->PLLCTL = CLK_PLLCTL_192MHz_HXT;
926 }
927 else
928 {
929 CLK->PLLCTL = CLK_PLLCTL_192MHz_HIRC;
930 }
931
932 /* Wait for PLL clock stable */
934
935 /* Actual PLL output clock frequency */
936 u32PllClk = CLK_GetPLLClockFreq();
937 }
938
939 return u32PllClk;
940}
941
950{
951 CLK->PLLCTL |= CLK_PLLCTL_PD_Msk;
952}
953
954
968uint32_t CLK_WaitClockReady(uint32_t u32ClkMask)
969{
970 uint32_t u32TimeOutCnt = SystemCoreClock / 2;
971 uint32_t u32Ret = 1U;
972
974 while((CLK->STATUS & u32ClkMask) != u32ClkMask)
975 {
976 if(--u32TimeOutCnt == 0)
977 {
978 u32Ret = 0U;
979 break;
980 }
981 }
982
983 if(u32TimeOutCnt == 0)
985
986 return u32Ret;
987}
988
1003void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count)
1004{
1005 /* Set System Tick counter disabled */
1006 SysTick->CTRL = 0UL;
1007
1008 /* Set System Tick clock source */
1009 if( u32ClkSrc == CLK_CLKSEL0_STCLKSEL_HCLK )
1010 {
1011 SysTick->CTRL |= SysTick_CTRL_CLKSOURCE_Msk;
1012 }
1013 else
1014 {
1015 CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_STCLKSEL_Msk) | u32ClkSrc;
1016 }
1017
1018 /* Set System Tick reload value */
1019 SysTick->LOAD = u32Count;
1020
1021 /* Clear System Tick current value and counter flag */
1022 SysTick->VAL = 0UL;
1023
1024 /* Set System Tick interrupt enabled and counter enabled */
1025 SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk;
1026}
1027
1035{
1036 /* Set System Tick counter disabled */
1037 SysTick->CTRL = 0UL;
1038}
1039
1040
1055void CLK_SetPowerDownMode(uint32_t u32PDMode)
1056{
1057 if ((SYS->CSERVER & SYS_CSERVER_VERSION_Msk) == 0x1) // M480LD
1058 {
1059 if(u32PDMode == CLK_PMUCTL_PDMSEL_SPD0)
1060 {
1061 u32PDMode = CLK_PMUCTL_PDMSEL_SPD0;
1062 CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_SRETSEL_Msk)) | CLK_SPDSRETSEL_16K;
1063 }
1064 else if(u32PDMode == CLK_PMUCTL_PDMSEL_SPD1)
1065 {
1066 u32PDMode = CLK_PMUCTL_PDMSEL_SPD0;
1067 CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_SRETSEL_Msk)) | CLK_SPDSRETSEL_NO;
1068 }
1069 }
1070 else
1071 {
1072 /* Enable LIRC clock before entering to Standby Power-down Mode */
1073 if((u32PDMode == CLK_PMUCTL_PDMSEL_SPD0) || (u32PDMode == CLK_PMUCTL_PDMSEL_SPD1))
1074 {
1075 /* Enable LIRC clock */
1076 CLK->PWRCTL |= CLK_PWRCTL_LIRCEN_Msk;
1077
1078 /* Wait for LIRC clock stable */
1080 }
1081 }
1082
1083 CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_PDMSEL_Msk)) | u32PDMode;
1084}
1085
1086
1111void CLK_EnableDPDWKPin(uint32_t u32TriggerType)
1112{
1113 uint32_t u32Pin1, u32Pin2, u32Pin3, u32Pin4;
1114
1115 if ((SYS->CSERVER & SYS_CSERVER_VERSION_Msk) == 0x1) // M480LD
1116 {
1117
1118 u32Pin1 = ((u32TriggerType) & CLK_PMUCTL_WKPINEN1_Msk);
1119 u32Pin2 = ((u32TriggerType) & CLK_PMUCTL_WKPINEN2_Msk);
1120 u32Pin3 = ((u32TriggerType) & CLK_PMUCTL_WKPINEN3_Msk);
1121 u32Pin4 = ((u32TriggerType) & CLK_PMUCTL_WKPINEN4_Msk);
1122
1123 if(u32Pin1)
1124 {
1125 CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_WKPINEN1_Msk)) | u32TriggerType;
1126 }
1127 else if(u32Pin2)
1128 {
1129 CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_WKPINEN2_Msk)) | u32TriggerType;
1130 }
1131 else if(u32Pin3)
1132 {
1133 CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_WKPINEN3_Msk)) | u32TriggerType;
1134 }
1135 else if(u32Pin4)
1136 {
1137 CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_WKPINEN4_Msk)) | u32TriggerType;
1138 }
1139 else
1140 {
1141 CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_WKPINEN_Msk)) | u32TriggerType;
1142 }
1143 }
1144 else
1145 {
1146 CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_WKPINEN_Msk)) | u32TriggerType;
1147 }
1148}
1149
1159uint32_t CLK_GetPMUWKSrc(void)
1160{
1161 return (CLK->PMUSTS);
1162}
1163
1180void CLK_EnableSPDWKPin(uint32_t u32Port, uint32_t u32Pin, uint32_t u32TriggerType, uint32_t u32DebounceEn)
1181{
1182 uint32_t u32tmpAddr = 0UL;
1183 uint32_t u32tmpVal = 0UL;
1184
1185 /* GPx Stand-by Power-down Wake-up Pin Select */
1186 u32tmpAddr = (uint32_t)&CLK->PASWKCTL;
1187 u32tmpAddr += (0x4UL * u32Port);
1188
1189 u32tmpVal = inpw((uint32_t *)u32tmpAddr);
1191 (u32Pin << CLK_PASWKCTL_WKPSEL_Pos) | u32TriggerType | u32DebounceEn | CLK_SPDWKPIN_ENABLE;
1192 outpw((uint32_t *)u32tmpAddr, u32tmpVal);
1193}
1194
1202{
1203 uint32_t u32PllFreq = 0UL, u32PllReg;
1204 uint32_t u32FIN, u32NF, u32NR, u32NO;
1205 uint8_t au8NoTbl[4] = {1U, 2U, 2U, 4U};
1206
1207 u32PllReg = CLK->PLLCTL;
1208
1209 if(u32PllReg & (CLK_PLLCTL_PD_Msk | CLK_PLLCTL_OE_Msk))
1210 {
1211 u32PllFreq = 0UL; /* PLL is in power down mode or fix low */
1212 }
1213 else if((u32PllReg & CLK_PLLCTL_BP_Msk) == CLK_PLLCTL_BP_Msk)
1214 {
1216 {
1217 u32FIN = __HIRC; /* PLL source clock from HIRC */
1218 }
1219 else
1220 {
1221 u32FIN = __HXT; /* PLL source clock from HXT */
1222 }
1223
1224 u32PllFreq = u32FIN;
1225 }
1226 else
1227 {
1229 {
1230 u32FIN = __HIRC; /* PLL source clock from HIRC */
1231 }
1232 else
1233 {
1234 u32FIN = __HXT; /* PLL source clock from HXT */
1235 }
1236 /* PLL is output enabled in normal work mode */
1237 u32NO = au8NoTbl[((u32PllReg & CLK_PLLCTL_OUTDIV_Msk) >> CLK_PLLCTL_OUTDIV_Pos)];
1238 u32NF = ((u32PllReg & CLK_PLLCTL_FBDIV_Msk) >> CLK_PLLCTL_FBDIV_Pos) + 2UL;
1239 u32NR = ((u32PllReg & CLK_PLLCTL_INDIV_Msk) >> CLK_PLLCTL_INDIV_Pos) + 1UL;
1240
1241 /* u32FIN is shifted 2 bits to avoid overflow */
1242 u32PllFreq = (((u32FIN >> 2) * u32NF) / (u32NR * u32NO) << 2) * 2UL;
1243 }
1244
1245 return u32PllFreq;
1246}
1247
1287uint32_t CLK_GetModuleClockSource(uint32_t u32ModuleIdx)
1288{
1289 uint32_t u32sel = 0;
1290 uint32_t u32SelTbl[4] = {0x0, 0x4, 0x8, 0xC};
1291
1292 /* Get clock source selection setting */
1293 if(u32ModuleIdx == EPWM0_MODULE)
1294 return ((CLK->CLKSEL2 & CLK_CLKSEL2_EPWM0SEL_Msk) >> CLK_CLKSEL2_EPWM0SEL_Pos);
1295 else if(u32ModuleIdx == EPWM1_MODULE)
1296 return ((CLK->CLKSEL2 & CLK_CLKSEL2_EPWM1SEL_Msk) >> CLK_CLKSEL2_EPWM1SEL_Pos);
1297 else if(u32ModuleIdx == BPWM0_MODULE)
1298 return ((CLK->CLKSEL2 & CLK_CLKSEL2_BPWM0SEL_Msk) >> CLK_CLKSEL2_BPWM0SEL_Pos);
1299 else if(u32ModuleIdx == BPWM1_MODULE)
1300 return ((CLK->CLKSEL2 & CLK_CLKSEL2_BPWM1SEL_Msk) >> CLK_CLKSEL2_BPWM1SEL_Pos);
1301 else if(MODULE_CLKSEL_Msk(u32ModuleIdx) != MODULE_NoMsk)
1302 {
1303 /* Get clock select control register address */
1304 u32sel = (uint32_t)&CLK->CLKSEL0 + (u32SelTbl[MODULE_CLKSEL(u32ModuleIdx)]);
1305 /* Get clock source selection setting */
1306 return ((M32(u32sel) & (MODULE_CLKSEL_Msk(u32ModuleIdx) << MODULE_CLKSEL_Pos(u32ModuleIdx))) >> MODULE_CLKSEL_Pos(u32ModuleIdx));
1307 }
1308 else
1309 return 0;
1310}
1311
1336uint32_t CLK_GetModuleClockDivider(uint32_t u32ModuleIdx)
1337{
1338 uint32_t u32div = 0;
1339 uint32_t u32DivTbl[4] = {0x0, 0x4, 0xc, 0x10};
1340
1341 if(MODULE_CLKDIV_Msk(u32ModuleIdx) != MODULE_NoMsk)
1342 {
1343 /* Get clock divider control register address */
1344 u32div = (uint32_t)&CLK->CLKDIV0 + (u32DivTbl[MODULE_CLKDIV(u32ModuleIdx)]);
1345 if ((SYS->CSERVER & SYS_CSERVER_VERSION_Msk) == 0x1) // M480LD
1346 {
1347 if(MODULE_IP_EN_Pos_ENC(u32ModuleIdx) == 31U) //EADC1
1348 u32div = (uint32_t)&CLK->CLKDIV2;
1349 else if(MODULE_IP_EN_Pos_ENC(u32ModuleIdx) == 29U) //I2S0
1350 u32div = (uint32_t)&CLK->CLKDIV2;
1351 }
1352 /* Get clock divider number setting */
1353 return ((M32(u32div) & (MODULE_CLKDIV_Msk(u32ModuleIdx) << MODULE_CLKDIV_Pos(u32ModuleIdx))) >> MODULE_CLKDIV_Pos(u32ModuleIdx));
1354 }
1355 else
1356 return 0;
1357}
1358
1359 /* end of group CLK_EXPORTED_FUNCTIONS */
1361 /* end of group CLK_Driver */
1363 /* end of group Standard_Driver */
1365
1366/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
NuMicro peripheral access layer header file.
int32_t g_CLK_i32ErrCode
Definition: clk.c:20
#define CLKO_MODULE
Definition: clk.h:384
#define CLK_CLKSEL0_STCLKSEL_HCLK
Definition: clk.h:57
#define CLK_PCLKDIV_APB0DIV_DIV2
Definition: clk.h:303
#define CLK_PLLCTL_PLLSRC_HXT
Definition: clk.h:316
#define BPWM1_MODULE
Definition: clk.h:421
#define MODULE_NoMsk
Definition: clk.h:352
#define MODULE_CLKSEL_Msk(x)
Definition: clk.h:346
#define CLK_CLKDIV0_HCLK(x)
Definition: clk.h:250
#define CLK_CLKSEL0_HCLKSEL_HIRC
Definition: clk.h:50
#define CLK_PCLKDIV_APB0DIV_DIV8
Definition: clk.h:305
#define CLK_PLLCTL_192MHz_HIRC
Definition: clk.h:336
#define CLK_CLKSEL0_HCLKSEL_PLL
Definition: clk.h:48
#define CLK_PMUCTL_PDMSEL_SPD0
Definition: clk.h:436
#define EPWM0_MODULE
Definition: clk.h:418
#define CLK_PCLKDIV_APB1DIV_DIV2
Definition: clk.h:308
#define FREQ_125MHZ
Definition: clk.h:36
#define CLK_PLLCTL_PLLSRC_HIRC
Definition: clk.h:317
#define EPWM1_MODULE
Definition: clk.h:419
#define CLK_PCLKDIV_APB0DIV_DIV16
Definition: clk.h:306
#define MODULE_CLKSEL_Pos(x)
Definition: clk.h:347
#define FREQ_192MHZ
Definition: clk.h:38
#define CLK_PCLKDIV_APB0DIV_DIV4
Definition: clk.h:304
#define FREQ_50MHZ
Definition: clk.h:32
#define CLK_PCLKDIV_APB1DIV_DIV4
Definition: clk.h:309
#define CLK_SPDSRETSEL_16K
Definition: clk.h:519
#define CLK_PLLCTL_192MHz_HXT
Definition: clk.h:330
#define MODULE_CLKDIV_Pos(x)
Definition: clk.h:350
#define BPWM0_MODULE
Definition: clk.h:420
#define MODULE_IP_EN_Pos(x)
Definition: clk.h:351
#define MODULE_CLKDIV_Msk(x)
Definition: clk.h:349
#define CLK_PCLKDIV_APB0DIV_DIV1
Definition: clk.h:302
#define CLK_PCLKDIV_APB1DIV_DIV8
Definition: clk.h:310
#define CLK_PCLKDIV_APB1DIV_DIV16
Definition: clk.h:311
#define CLK_PCLKDIV_APB1DIV_DIV1
Definition: clk.h:307
#define CLK_SPDSRETSEL_NO
Definition: clk.h:518
#define MODULE_CLKDIV(x)
Definition: clk.h:348
#define MODULE_APBCLK(x)
Definition: clk.h:344
#define CLK_PMUCTL_PDMSEL_SPD1
Definition: clk.h:437
#define CLK_SPDWKPIN_ENABLE
Definition: clk.h:512
#define MODULE_IP_EN_Pos_ENC(x)
Definition: clk.h:362
#define CLK_TIMEOUT_ERR
Definition: clk.h:537
#define FREQ_500MHZ
Definition: clk.h:41
#define MODULE_CLKSEL(x)
Definition: clk.h:345
void CLK_Idle(void)
Enter to Idle mode.
Definition: clk.c:104
void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc)
Set SysTick clock source.
Definition: clk.c:577
uint32_t CLK_GetHCLKFreq(void)
Get HCLK frequency.
Definition: clk.c:246
uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq)
Set PLL frequency.
Definition: clk.c:792
void CLK_DisableCKO(void)
Disable clock divider output function.
Definition: clk.c:32
void CLK_EnableDPDWKPin(uint32_t u32TriggerType)
Set Wake-up pin trigger type at Deep Power down mode.
Definition: clk.c:1111
void CLK_EnableModuleClock(uint32_t u32ModuleIdx)
Enable module clock.
Definition: clk.c:687
void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En)
This function enable clock divider output module clock, enable clock divider output function and set ...
Definition: clk.c:55
void CLK_DisableModuleClock(uint32_t u32ModuleIdx)
Disable module clock.
Definition: clk.c:770
uint32_t CLK_WaitClockReady(uint32_t u32ClkMask)
This function check selected clock source status.
Definition: clk.c:968
uint32_t CLK_GetPMUWKSrc(void)
Get power manager wake up source.
Definition: clk.c:1159
uint32_t CLK_GetLXTFreq(void)
Get external low speed crystal clock frequency.
Definition: clk.c:145
uint32_t CLK_GetPCLK1Freq(void)
Get PCLK1 frequency.
Definition: clk.c:206
void CLK_PowerDown(void)
Enter to Power-down mode.
Definition: clk.c:74
uint32_t CLK_GetPCLK0Freq(void)
Get PCLK0 frequency.
Definition: clk.c:166
uint32_t CLK_GetModuleClockDivider(uint32_t u32ModuleIdx)
Get selected module clock divider number.
Definition: clk.c:1336
void CLK_DisablePLL(void)
Disable PLL.
Definition: clk.c:949
uint32_t CLK_GetCPUFreq(void)
Get CPU frequency.
Definition: clk.c:259
uint32_t CLK_GetModuleClockSource(uint32_t u32ModuleIdx)
Get selected module clock source.
Definition: clk.c:1287
void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv)
This function set HCLK clock source and HCLK clock divider.
Definition: clk.c:335
void CLK_SetPowerDownMode(uint32_t u32PDMode)
Power-down mode selected.
Definition: clk.c:1055
void CLK_DisableXtalRC(uint32_t u32ClkMask)
Disable clock source.
Definition: clk.c:610
void CLK_DisableSysTick(void)
Disable System Tick counter.
Definition: clk.c:1034
void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv)
This function set selected module clock source and module clock divider.
Definition: clk.c:505
void CLK_EnableXtalRC(uint32_t u32ClkMask)
Enable clock source.
Definition: clk.c:594
void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count)
Enable System Tick counter.
Definition: clk.c:1003
uint32_t CLK_SetCoreClock(uint32_t u32Hclk)
Set HCLK frequency.
Definition: clk.c:273
uint32_t CLK_GetPLLClockFreq(void)
Get PLL clock frequency.
Definition: clk.c:1201
void CLK_EnableSPDWKPin(uint32_t u32Port, uint32_t u32Pin, uint32_t u32TriggerType, uint32_t u32DebounceEn)
Set specified GPIO as wake up source at Stand-by Power down mode.
Definition: clk.c:1180
uint32_t CLK_GetHXTFreq(void)
Get external high speed crystal clock frequency.
Definition: clk.c:122
#define M32(addr)
Get a 32-bit unsigned value from specified address.
Definition: M480.h:493
#define outpw(port, value)
Set a 32-bit unsigned value to specified I/O port.
Definition: M480.h:502
#define inpw(port)
Get a 32-bit unsigned value from specified I/O port.
Definition: M480.h:510
#define CLK
Definition: M480.h:368
#define SYS
Definition: M480.h:367
#define CLK_PMUCTL_WKPINEN4_Msk
Definition: clk_reg.h:2808
#define SYS_CSERVER_VERSION_Msk
Definition: sys_reg.h:6034
#define CLK_PWRCTL_LIRCEN_Msk
Definition: clk_reg.h:2286
#define CLK_PMUCTL_WKPINEN2_Msk
Definition: clk_reg.h:2802
#define CLK_PASWKCTL_DBEN_Msk
Definition: clk_reg.h:2874
#define CLK_PASWKCTL_PRWKEN_Msk
Definition: clk_reg.h:2865
#define CLK_PWRCTL_LXTEN_Msk
Definition: clk_reg.h:2280
#define CLK_PLLCTL_INDIV_Pos
Definition: clk_reg.h:2687
#define CLK_PLLCTL_BP_Msk
Definition: clk_reg.h:2697
#define CLK_PMUCTL_PDMSEL_Msk
Definition: clk_reg.h:2775
#define CLK_PLLCTL_FBDIV_Msk
Definition: clk_reg.h:2685
#define CLK_CLKSEL2_EPWM1SEL_Msk
Definition: clk_reg.h:2556
#define CLK_PCLKDIV_APB1DIV_Msk
Definition: clk_reg.h:2682
#define CLK_PMUCTL_WKPINEN1_Msk
Definition: clk_reg.h:2799
#define CLK_STATUS_PLLSTB_Msk
Definition: clk_reg.h:2715
#define CLK_PWRCTL_PDEN_Msk
Definition: clk_reg.h:2298
#define CLK_CLKOCTL_CLKOEN_Msk
Definition: clk_reg.h:2733
#define CLK_STATUS_LIRCSTB_Msk
Definition: clk_reg.h:2718
#define CLK_PLLCTL_INDIV_Msk
Definition: clk_reg.h:2688
#define CLK_CLKSEL0_HCLKSEL_Msk
Definition: clk_reg.h:2508
#define CLK_PLLCTL_PD_Msk
Definition: clk_reg.h:2694
#define CLK_PWRCTL_HIRCEN_Msk
Definition: clk_reg.h:2283
#define CLK_PLLCTL_OUTDIV_Pos
Definition: clk_reg.h:2690
#define CLK_PLLCTL_OUTDIV_Msk
Definition: clk_reg.h:2691
#define CLK_PMUCTL_WKPINEN_Msk
Definition: clk_reg.h:2790
#define CLK_PCLKDIV_APB0DIV_Msk
Definition: clk_reg.h:2679
#define CLK_CLKSEL2_BPWM1SEL_Pos
Definition: clk_reg.h:2570
#define CLK_CLKSEL2_BPWM0SEL_Pos
Definition: clk_reg.h:2567
#define CLK_PASWKCTL_WKEN_Msk
Definition: clk_reg.h:2862
#define CLK_PWRCTL_HXTEN_Msk
Definition: clk_reg.h:2277
#define CLK_PASWKCTL_WKPSEL_Pos
Definition: clk_reg.h:2870
#define CLK_CLKSEL2_EPWM1SEL_Pos
Definition: clk_reg.h:2555
#define CLK_STATUS_HXTSTB_Msk
Definition: clk_reg.h:2709
#define CLK_PLLCTL_OE_Msk
Definition: clk_reg.h:2700
#define CLK_PMUCTL_SRETSEL_Msk
Definition: clk_reg.h:2781
#define CLK_PASWKCTL_PFWKEN_Msk
Definition: clk_reg.h:2868
#define CLK_CLKSEL2_BPWM1SEL_Msk
Definition: clk_reg.h:2571
#define CLK_STATUS_HIRCSTB_Msk
Definition: clk_reg.h:2721
#define CLK_PLLCTL_FBDIV_Pos
Definition: clk_reg.h:2684
#define CLK_CLKOCTL_DIV1EN_Pos
Definition: clk_reg.h:2735
#define CLK_CLKSEL2_EPWM0SEL_Pos
Definition: clk_reg.h:2552
#define CLK_CLKSEL2_EPWM0SEL_Msk
Definition: clk_reg.h:2553
#define CLK_PMUCTL_WKPINEN3_Msk
Definition: clk_reg.h:2805
#define CLK_PASWKCTL_WKPSEL_Msk
Definition: clk_reg.h:2871
#define CLK_CLKSEL2_BPWM0SEL_Msk
Definition: clk_reg.h:2568
#define __HIRC
Definition: system_M480.h:36
#define __HXT
Definition: system_M480.h:29
uint32_t SystemCoreClock
Definition: system_M480.c:21
#define __LXT
Definition: system_M480.h:33
void SystemCoreClockUpdate(void)
Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
Definition: system_M480.c:29