55void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En)
76 uint32_t u32HIRCTRIMCTL;
79 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
85 u32HIRCTRIMCTL =
SYS->IRCTCTL;
88 SYS->IRCTCTL &= (~SYS_IRCTCTL_FREQSEL_Msk);
94 SYS->IRCTCTL = u32HIRCTRIMCTL;
107 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
110 CLK->PWRCTL &= ~CLK_PWRCTL_PDEN_Msk;
290 CLK->CLKDIV0 &= (~CLK_CLKDIV0_HCLKDIV_Msk);
312 if(u32HIRCSTB == 0UL)
314 CLK->PWRCTL &= ~CLK_PWRCTL_HIRCEN_Msk;
348 CLK->CLKDIV0 = (
CLK->CLKDIV0 & (~CLK_CLKDIV0_HCLKDIV_Msk)) | u32ClkDiv;
351 CLK->CLKSEL0 = (
CLK->CLKSEL0 & (~CLK_CLKSEL0_HCLKSEL_Msk)) | u32ClkSrc;
357 if(u32HIRCSTB == 0UL)
359 CLK->PWRCTL &= ~CLK_PWRCTL_HIRCEN_Msk;
507 uint32_t u32sel = 0U, u32div = 0U;
516 u32div = (uint32_t)&
CLK->CLKDIV2;
520 u32div = (uint32_t)&
CLK->CLKDIV2;
524 u32div = (uint32_t)&
CLK->CLKDIV3;
528 u32div = (uint32_t)&
CLK->CLKDIV4;
540 u32div = (uint32_t)&
CLK->CLKDIV3;
544 u32div = (uint32_t)&
CLK->CLKDIV4;
579 CLK->CLKSEL0 = (
CLK->CLKSEL0 & ~CLK_CLKSEL0_STCLKSEL_Msk) | u32ClkSrc;
596 CLK->PWRCTL |= u32ClkMask;
612 CLK->PWRCTL &= ~u32ClkMask;
689 uint32_t u32tmpVal = 0UL, u32tmpAddr = 0UL;
692 u32tmpAddr = (uint32_t)&
CLK->AHBCLK;
695 *(
volatile uint32_t *)u32tmpAddr |= u32tmpVal;
772 uint32_t u32tmpVal = 0UL, u32tmpAddr = 0UL;
775 u32tmpAddr = (uint32_t)&
CLK->AHBCLK;
778 *(uint32_t *)u32tmpAddr &= u32tmpVal;
794 uint32_t u32PllSrcClk, u32NR, u32NF, u32NO, u32CLK_SRC, u32PllClk;
795 uint32_t u32Tmp, u32Tmp2, u32Tmp3, u32Min, u32MinNF, u32MinNR, u32MinNO, u32basFreq;
811 u32PllSrcClk =
__HXT;
815 if((u32PllSrcClk >= 4000000UL) && (u32PllSrcClk <= 8000000UL))
842 u32Min = (uint32_t) - 1;
846 u32basFreq = u32PllFreq;
848 for(u32NO = 1UL; u32NO <= 4UL; u32NO++)
861 u32PllFreq = u32basFreq << 2;
863 else if(u32NO == 2UL)
865 u32PllFreq = u32basFreq << 1;
871 for(u32NR = 1UL; u32NR <= 32UL; u32NR++)
879 u32Tmp = u32PllSrcClk / u32NR;
880 if((u32Tmp >= 4000000UL) && (u32Tmp <= 8000000UL))
882 for(u32NF = 2UL; u32NF <= 513UL; u32NF++)
885 u32Tmp2 = (((u32Tmp * 2UL) >> 2) * u32NF);
889 u32Tmp3 = (u32Tmp2 > (u32PllFreq>>2)) ? u32Tmp2 - (u32PllFreq>>2) : (u32PllFreq>>2) - u32Tmp2;
911 CLK->PLLCTL = u32CLK_SRC | ((u32MinNO - 1UL) << 14) | ((u32MinNR - 1UL) << 9) | (u32MinNF - 2UL);
917 u32PllClk = u32PllSrcClk / (u32MinNO * (u32MinNR)) * (u32MinNF) * 2UL;
971 uint32_t u32Ret = 1U;
974 while((
CLK->STATUS & u32ClkMask) != u32ClkMask)
976 if(--u32TimeOutCnt == 0)
983 if(u32TimeOutCnt == 0)
1006 SysTick->CTRL = 0UL;
1011 SysTick->CTRL |= SysTick_CTRL_CLKSOURCE_Msk;
1015 CLK->CLKSEL0 = (
CLK->CLKSEL0 & ~CLK_CLKSEL0_STCLKSEL_Msk) | u32ClkSrc;
1019 SysTick->LOAD = u32Count;
1025 SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk;
1037 SysTick->CTRL = 0UL;
1113 uint32_t u32Pin1, u32Pin2, u32Pin3, u32Pin4;
1161 return (
CLK->PMUSTS);
1180void CLK_EnableSPDWKPin(uint32_t u32Port, uint32_t u32Pin, uint32_t u32TriggerType, uint32_t u32DebounceEn)
1182 uint32_t u32tmpAddr = 0UL;
1183 uint32_t u32tmpVal = 0UL;
1186 u32tmpAddr = (uint32_t)&
CLK->PASWKCTL;
1187 u32tmpAddr += (0x4UL * u32Port);
1189 u32tmpVal =
inpw((uint32_t *)u32tmpAddr);
1192 outpw((uint32_t *)u32tmpAddr, u32tmpVal);
1203 uint32_t u32PllFreq = 0UL, u32PllReg;
1204 uint32_t u32FIN, u32NF, u32NR, u32NO;
1205 uint8_t au8NoTbl[4] = {1U, 2U, 2U, 4U};
1207 u32PllReg =
CLK->PLLCTL;
1224 u32PllFreq = u32FIN;
1242 u32PllFreq = (((u32FIN >> 2) * u32NF) / (u32NR * u32NO) << 2) * 2UL;
1289 uint32_t u32sel = 0;
1290 uint32_t u32SelTbl[4] = {0x0, 0x4, 0x8, 0xC};
1304 u32sel = (uint32_t)&
CLK->CLKSEL0 + (u32SelTbl[
MODULE_CLKSEL(u32ModuleIdx)]);
1338 uint32_t u32div = 0;
1339 uint32_t u32DivTbl[4] = {0x0, 0x4, 0xc, 0x10};
1344 u32div = (uint32_t)&
CLK->CLKDIV0 + (u32DivTbl[
MODULE_CLKDIV(u32ModuleIdx)]);
1348 u32div = (uint32_t)&
CLK->CLKDIV2;
1350 u32div = (uint32_t)&
CLK->CLKDIV2;
NuMicro peripheral access layer header file.
#define CLK_CLKSEL0_STCLKSEL_HCLK
#define CLK_PCLKDIV_APB0DIV_DIV2
#define CLK_PLLCTL_PLLSRC_HXT
#define MODULE_CLKSEL_Msk(x)
#define CLK_CLKDIV0_HCLK(x)
#define CLK_CLKSEL0_HCLKSEL_HIRC
#define CLK_PCLKDIV_APB0DIV_DIV8
#define CLK_PLLCTL_192MHz_HIRC
#define CLK_CLKSEL0_HCLKSEL_PLL
#define CLK_PMUCTL_PDMSEL_SPD0
#define CLK_PCLKDIV_APB1DIV_DIV2
#define CLK_PLLCTL_PLLSRC_HIRC
#define CLK_PCLKDIV_APB0DIV_DIV16
#define MODULE_CLKSEL_Pos(x)
#define CLK_PCLKDIV_APB0DIV_DIV4
#define CLK_PCLKDIV_APB1DIV_DIV4
#define CLK_SPDSRETSEL_16K
#define CLK_PLLCTL_192MHz_HXT
#define MODULE_CLKDIV_Pos(x)
#define MODULE_IP_EN_Pos(x)
#define MODULE_CLKDIV_Msk(x)
#define CLK_PCLKDIV_APB0DIV_DIV1
#define CLK_PCLKDIV_APB1DIV_DIV8
#define CLK_PCLKDIV_APB1DIV_DIV16
#define CLK_PCLKDIV_APB1DIV_DIV1
#define CLK_SPDSRETSEL_NO
#define CLK_PMUCTL_PDMSEL_SPD1
#define CLK_SPDWKPIN_ENABLE
#define MODULE_IP_EN_Pos_ENC(x)
void CLK_Idle(void)
Enter to Idle mode.
void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc)
Set SysTick clock source.
uint32_t CLK_GetHCLKFreq(void)
Get HCLK frequency.
uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq)
Set PLL frequency.
void CLK_DisableCKO(void)
Disable clock divider output function.
void CLK_EnableDPDWKPin(uint32_t u32TriggerType)
Set Wake-up pin trigger type at Deep Power down mode.
void CLK_EnableModuleClock(uint32_t u32ModuleIdx)
Enable module clock.
void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En)
This function enable clock divider output module clock, enable clock divider output function and set ...
void CLK_DisableModuleClock(uint32_t u32ModuleIdx)
Disable module clock.
uint32_t CLK_WaitClockReady(uint32_t u32ClkMask)
This function check selected clock source status.
uint32_t CLK_GetPMUWKSrc(void)
Get power manager wake up source.
uint32_t CLK_GetLXTFreq(void)
Get external low speed crystal clock frequency.
uint32_t CLK_GetPCLK1Freq(void)
Get PCLK1 frequency.
void CLK_PowerDown(void)
Enter to Power-down mode.
uint32_t CLK_GetPCLK0Freq(void)
Get PCLK0 frequency.
uint32_t CLK_GetModuleClockDivider(uint32_t u32ModuleIdx)
Get selected module clock divider number.
void CLK_DisablePLL(void)
Disable PLL.
uint32_t CLK_GetCPUFreq(void)
Get CPU frequency.
uint32_t CLK_GetModuleClockSource(uint32_t u32ModuleIdx)
Get selected module clock source.
void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv)
This function set HCLK clock source and HCLK clock divider.
void CLK_SetPowerDownMode(uint32_t u32PDMode)
Power-down mode selected.
void CLK_DisableXtalRC(uint32_t u32ClkMask)
Disable clock source.
void CLK_DisableSysTick(void)
Disable System Tick counter.
void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv)
This function set selected module clock source and module clock divider.
void CLK_EnableXtalRC(uint32_t u32ClkMask)
Enable clock source.
void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count)
Enable System Tick counter.
uint32_t CLK_SetCoreClock(uint32_t u32Hclk)
Set HCLK frequency.
uint32_t CLK_GetPLLClockFreq(void)
Get PLL clock frequency.
void CLK_EnableSPDWKPin(uint32_t u32Port, uint32_t u32Pin, uint32_t u32TriggerType, uint32_t u32DebounceEn)
Set specified GPIO as wake up source at Stand-by Power down mode.
uint32_t CLK_GetHXTFreq(void)
Get external high speed crystal clock frequency.
#define M32(addr)
Get a 32-bit unsigned value from specified address.
#define outpw(port, value)
Set a 32-bit unsigned value to specified I/O port.
#define inpw(port)
Get a 32-bit unsigned value from specified I/O port.
#define CLK_PMUCTL_WKPINEN4_Msk
#define SYS_CSERVER_VERSION_Msk
#define CLK_PWRCTL_LIRCEN_Msk
#define CLK_PMUCTL_WKPINEN2_Msk
#define CLK_PASWKCTL_DBEN_Msk
#define CLK_PASWKCTL_PRWKEN_Msk
#define CLK_PWRCTL_LXTEN_Msk
#define CLK_PLLCTL_INDIV_Pos
#define CLK_PLLCTL_BP_Msk
#define CLK_PMUCTL_PDMSEL_Msk
#define CLK_PLLCTL_FBDIV_Msk
#define CLK_CLKSEL2_EPWM1SEL_Msk
#define CLK_PCLKDIV_APB1DIV_Msk
#define CLK_PMUCTL_WKPINEN1_Msk
#define CLK_STATUS_PLLSTB_Msk
#define CLK_PWRCTL_PDEN_Msk
#define CLK_CLKOCTL_CLKOEN_Msk
#define CLK_STATUS_LIRCSTB_Msk
#define CLK_PLLCTL_INDIV_Msk
#define CLK_CLKSEL0_HCLKSEL_Msk
#define CLK_PLLCTL_PD_Msk
#define CLK_PWRCTL_HIRCEN_Msk
#define CLK_PLLCTL_OUTDIV_Pos
#define CLK_PLLCTL_OUTDIV_Msk
#define CLK_PMUCTL_WKPINEN_Msk
#define CLK_PCLKDIV_APB0DIV_Msk
#define CLK_CLKSEL2_BPWM1SEL_Pos
#define CLK_CLKSEL2_BPWM0SEL_Pos
#define CLK_PASWKCTL_WKEN_Msk
#define CLK_PWRCTL_HXTEN_Msk
#define CLK_PASWKCTL_WKPSEL_Pos
#define CLK_CLKSEL2_EPWM1SEL_Pos
#define CLK_STATUS_HXTSTB_Msk
#define CLK_PLLCTL_OE_Msk
#define CLK_PMUCTL_SRETSEL_Msk
#define CLK_PASWKCTL_PFWKEN_Msk
#define CLK_CLKSEL2_BPWM1SEL_Msk
#define CLK_STATUS_HIRCSTB_Msk
#define CLK_PLLCTL_FBDIV_Pos
#define CLK_CLKOCTL_DIV1EN_Pos
#define CLK_CLKSEL2_EPWM0SEL_Pos
#define CLK_CLKSEL2_EPWM0SEL_Msk
#define CLK_PMUCTL_WKPINEN3_Msk
#define CLK_PASWKCTL_WKPSEL_Msk
#define CLK_CLKSEL2_BPWM0SEL_Msk
void SystemCoreClockUpdate(void)
Updates the SystemCoreClock with current core Clock retrieved from cpu registers.