M480 BSP
V3.05.006
The Board Support Package for M480 Series
Device
Nuvoton
M480
Include
ccap_reg.h
Go to the documentation of this file.
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/**************************************************************************/
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#ifndef __CCAP_REG_H__
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#define __CCAP_REG_H__
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#if defined ( __CC_ARM )
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#pragma anon_unions
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#endif
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typedef
struct
{
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__IO uint32_t
CTL
;
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__IO uint32_t
PAR
;
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__IO uint32_t
INT
;
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__IO uint32_t
POSTERIZE
;
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__IO uint32_t
MD
;
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__IO uint32_t
MDADDR
;
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__IO uint32_t
MDYADDR
;
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__IO uint32_t
SEPIA
;
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__IO uint32_t
CWSP
;
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__IO uint32_t
CWS
;
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__IO uint32_t
PKTSL
;
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__IO uint32_t
PLNSL
;
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__IO uint32_t
FRCTL
;
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__IO uint32_t
STRIDE
;
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uint32_t RESERVE0[1];
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__IO uint32_t
FIFOTH
;
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__IO uint32_t
CMPADDR
;
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__IO uint32_t
LUMA_Y1_THD
;
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__IO uint32_t
PKTSM
;
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uint32_t RESERVE2[5];
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__IO uint32_t
PKTBA0
;
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}
CCAP_T
;
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#define CCAP_CTL_CCAPEN_Pos (0)
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#define CCAP_CTL_CCAPEN_Msk (0x1ul << CCAP_CTL_CCAPEN_Pos)
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#define CCAP_CTL_ADDRSW_Pos (3)
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#define CCAP_CTL_ADDRSW_Msk (0x1ul << CCAP_CTL_ADDRSW_Pos)
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#define CCAP_CTL_PLNEN_Pos (5)
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#define CCAP_CTL_PLNEN_Msk (0x1ul << CCAP_CTL_PLNEN_Pos)
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#define CCAP_CTL_PKTEN_Pos (6)
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#define CCAP_CTL_PKTEN_Msk (0x1ul << CCAP_CTL_PKTEN_Pos)
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#define CCAP_CTL_MONO_Pos (7)
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#define CCAP_CTL_MONO_Msk (0x1ul << CCAP_CTL_MONO_Pos)
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#define CCAP_CTL_SHUTTER_Pos (16)
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#define CCAP_CTL_SHUTTER_Msk (0x1ul << CCAP_CTL_SHUTTER_Pos)
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#define CCAP_CTL_MY4_SWAP_Pos (17)
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#define CCAP_CTL_MY4_SWAP_Msk (0x1ul << CCAP_CTL_MY4_SWAP_Pos)
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#define CCAP_CTL_MY8_MY4_Pos (18)
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#define CCAP_CTL_MY8_MY4_Msk (0x1ul << CCAP_CTL_MY8_MY4_Pos)
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#define CCAP_CTL_Luma_Y_One_Pos (19)
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#define CCAP_CTL_Luma_Y_One_Msk (0x1ul << CCAP_CTL_Luma_Y_One_Pos)
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#define CCAP_CTL_UPDATE_Pos (20)
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#define CCAP_CTL_UPDATE_Msk (0x1ul << CCAP_CTL_UPDATE_Pos)
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#define CCAP_CTL_VPRST_Pos (24)
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#define CCAP_CTL_VPRST_Msk (0x1ul << CCAP_CTL_VPRST_Pos)
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#define CCAP_PAR_INFMT_Pos (0)
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#define CCAP_PAR_INFMT_Msk (0x1ul << CCAP_PAR_INFMT_Pos)
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#define CCAP_PAR_SENTYPE_Pos (1)
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#define CCAP_PAR_SENTYPE_Msk (0x1ul << CCAP_PAR_SENTYPE_Pos)
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#define CCAP_PAR_INDATORD_Pos (2)
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#define CCAP_PAR_INDATORD_Msk (0x3ul << CCAP_PAR_INDATORD_Pos)
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#define CCAP_PAR_OUTFMT_Pos (4)
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#define CCAP_PAR_OUTFMT_Msk (0x3ul << CCAP_PAR_OUTFMT_Pos)
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#define CCAP_PAR_RANGE_Pos (6)
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#define CCAP_PAR_RANGE_Msk (0x1ul << CCAP_PAR_RANGE_Pos)
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#define CCAP_PAR_PLNFMT_Pos (7)
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#define CCAP_PAR_PLNFMT_Msk (0x1ul << CCAP_PAR_PLNFMT_Pos)
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#define CCAP_PAR_PCLKP_Pos (8)
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#define CCAP_PAR_PCLKP_Msk (0x1ul << CCAP_PAR_PCLKP_Pos)
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#define CCAP_PAR_HSP_Pos (9)
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#define CCAP_PAR_HSP_Msk (0x1ul << CCAP_PAR_HSP_Pos)
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#define CCAP_PAR_VSP_Pos (10)
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#define CCAP_PAR_VSP_Msk (0x1ul << CCAP_PAR_VSP_Pos)
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#define CCAP_PAR_COLORCTL_Pos (11)
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#define CCAP_PAR_COLORCTL_Msk (0x3ul << CCAP_PAR_COLORCTL_Pos)
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#define CCAP_PAR_FBB_Pos (18)
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#define CCAP_PAR_FBB_Msk (0x1ul << CCAP_PAR_FBB_Pos)
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#define CCAP_INT_VINTF_Pos (0)
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#define CCAP_INT_VINTF_Msk (0x1ul << CCAP_INT_VINTF_Pos)
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#define CCAP_INT_MEINTF_Pos (1)
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#define CCAP_INT_MEINTF_Msk (0x1ul << CCAP_INT_MEINTF_Pos)
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#define CCAP_INT_ADDRMINTF_Pos (3)
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#define CCAP_INT_ADDRMINTF_Msk (0x1ul << CCAP_INT_ADDRMINTF_Pos)
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#define CCAP_INT_MDINTF_Pos (4)
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#define CCAP_INT_MDINTF_Msk (0x1ul << CCAP_INT_MDINTF_Pos)
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#define CCAP_INT_VIEN_Pos (16)
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#define CCAP_INT_VIEN_Msk (0x1ul << CCAP_INT_VIEN_Pos)
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#define CCAP_INT_MEIEN_Pos (17)
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#define CCAP_INT_MEIEN_Msk (0x1ul << CCAP_INT_MEIEN_Pos)
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#define CCAP_INT_ADDRMIEN_Pos (19)
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#define CCAP_INT_ADDRMIEN_Msk (0x1ul << CCAP_INT_ADDRMIEN_Pos)
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#define CCAP_CWSP_CWSADDRH_Pos (0)
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#define CCAP_CWSP_CWSADDRH_Msk (0xffful << CCAP_CWSP_CWSADDRH_Pos)
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#define CCAP_CWSP_CWSADDRV_Pos (16)
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#define CCAP_CWSP_CWSADDRV_Msk (0x7fful << CCAP_CWSP_CWSADDRV_Pos)
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#define CCAP_CWS_CWW_Pos (0)
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#define CCAP_CWS_CWW_Msk (0xffful << CCAP_CWS_CWW_Pos)
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#define CCAP_CWS_CWH_Pos (16)
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#define CCAP_CWS_CWH_Msk (0x7fful << CCAP_CWS_CWH_Pos)
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#define CCAP_PKTSL_PKTSHML_Pos (0)
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#define CCAP_PKTSL_PKTSHML_Msk (0xfful << CCAP_PKTSL_PKTSHML_Pos)
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#define CCAP_PKTSL_PKTSHNL_Pos (8)
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#define CCAP_PKTSL_PKTSHNL_Msk (0xfful << CCAP_PKTSL_PKTSHNL_Pos)
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#define CCAP_PKTSL_PKTSVML_Pos (16)
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#define CCAP_PKTSL_PKTSVML_Msk (0xfful << CCAP_PKTSL_PKTSVML_Pos)
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#define CCAP_PKTSL_PKTSVNL_Pos (24)
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#define CCAP_PKTSL_PKTSVNL_Msk (0xfful << CCAP_PKTSL_PKTSVNL_Pos)
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#define CCAP_FRCTL_FRM_Pos (0)
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#define CCAP_FRCTL_FRM_Msk (0x3ful << CCAP_FRCTL_FRM_Pos)
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#define CCAP_FRCTL_FRN_Pos (8)
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#define CCAP_FRCTL_FRN_Msk (0x3ful << CCAP_FRCTL_FRN_Pos)
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#define CCAP_STRIDE_PKTSTRIDE_Pos (0)
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#define CCAP_STRIDE_PKTSTRIDE_Msk (0x3ffful << CCAP_STRIDE_PKTSTRIDE_Pos)
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#define CCAP_STRIDE_PLNSTRIDE_Pos (16)
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#define CCAP_STRIDE_PLNSTRIDE_Msk (0x3ffful << CCAP_STRIDE_PLNSTRIDE_Pos)
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#define CCAP_FIFOTH_PLNVFTH_Pos (0)
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#define CCAP_FIFOTH_PLNVFTH_Msk (0xful << CCAP_FIFOTH_PLNVFTH_Pos)
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#define CCAP_FIFOTH_PLNUFTH_Pos (8)
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#define CCAP_FIFOTH_PLNUFTH_Msk (0xful << CCAP_FIFOTH_PLNUFTH_Pos)
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#define CCAP_FIFOTH_PLNYFTH_Pos (16)
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#define CCAP_FIFOTH_PLNYFTH_Msk (0x1ful << CCAP_FIFOTH_PLNYFTH_Pos)
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#define CCAP_FIFOTH_PKTFTH_Pos (24)
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#define CCAP_FIFOTH_PKTFTH_Msk (0x1ful << CCAP_FIFOTH_PKTFTH_Pos)
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#define CCAP_FIFOTH_OVF_Pos (31)
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#define CCAP_FIFOTH_OVF_Msk (0x1ul << CCAP_FIFOTH_OVF_Pos)
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#define CCAP_CMPADDR_CMPADDR_Pos (0)
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#define CCAP_CMPADDR_CMPADDR_Msk (0xfffffffful << CCAP_CMPADDR_CMPADDR_Pos)
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#define CCAP_PKTSM_PKTSHMH_Pos (0)
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#define CCAP_PKTSM_PKTSHMH_Msk (0xfful << CCAP_PKTSM_PKTSHMH_Pos)
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#define CCAP_PKTSM_PKTSHNH_Pos (8)
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#define CCAP_PKTSM_PKTSHNH_Msk (0xfful << CCAP_PKTSM_PKTSHNH_Pos)
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#define CCAP_PKTSM_PKTSVMH_Pos (16)
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#define CCAP_PKTSM_PKTSVMH_Msk (0xfful << CCAP_PKTSM_PKTSVMH_Pos)
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#define CCAP_PKTSM_PKTSVNH_Pos (24)
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#define CCAP_PKTSM_PKTSVNH_Msk (0xfful << CCAP_PKTSM_PKTSVNH_Pos)
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#define CCAP_PKTBA0_BASEADDR_Pos (0)
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#define CCAP_PKTBA0_BASEADDR_Msk (0xfffffffful << CCAP_PKTBA0_BASEADDR_Pos)
/* CCAP_CONST */
/* end of CCAP register group */
/* end of REGISTER group */
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#if defined ( __CC_ARM )
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#pragma no_anon_unions
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#endif
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#endif
/* __CCAP_REG_H__ */
CCAP_T
Definition:
ccap_reg.h:27
CCAP_T::MDYADDR
__IO uint32_t MDYADDR
Definition:
ccap_reg.h:697
CCAP_T::MDADDR
__IO uint32_t MDADDR
Definition:
ccap_reg.h:696
CCAP_T::CWSP
__IO uint32_t CWSP
Definition:
ccap_reg.h:699
CCAP_T::STRIDE
__IO uint32_t STRIDE
Definition:
ccap_reg.h:704
CCAP_T::SEPIA
__IO uint32_t SEPIA
Definition:
ccap_reg.h:698
CCAP_T::CMPADDR
__IO uint32_t CMPADDR
Definition:
ccap_reg.h:709
CCAP_T::CTL
__IO uint32_t CTL
Definition:
ccap_reg.h:691
CCAP_T::PKTBA0
__IO uint32_t PKTBA0
Definition:
ccap_reg.h:715
CCAP_T::CWS
__IO uint32_t CWS
Definition:
ccap_reg.h:700
CCAP_T::FIFOTH
__IO uint32_t FIFOTH
Definition:
ccap_reg.h:708
CCAP_T::FRCTL
__IO uint32_t FRCTL
Definition:
ccap_reg.h:703
CCAP_T::POSTERIZE
__IO uint32_t POSTERIZE
Definition:
ccap_reg.h:694
CCAP_T::INT
__IO uint32_t INT
Definition:
ccap_reg.h:693
CCAP_T::MD
__IO uint32_t MD
Definition:
ccap_reg.h:695
CCAP_T::PAR
__IO uint32_t PAR
Definition:
ccap_reg.h:692
CCAP_T::PKTSM
__IO uint32_t PKTSM
Definition:
ccap_reg.h:711
CCAP_T::PLNSL
__IO uint32_t PLNSL
Definition:
ccap_reg.h:702
CCAP_T::LUMA_Y1_THD
__IO uint32_t LUMA_Y1_THD
Definition:
ccap_reg.h:710
CCAP_T::PKTSL
__IO uint32_t PKTSL
Definition:
ccap_reg.h:701
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