M480 BSP
V3.05.006
The Board Support Package for M480 Series
Device
Nuvoton
M480
Include
qspi_reg.h
Go to the documentation of this file.
1
/**************************************************************************/
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#ifndef __QSPI_REG_H__
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#define __QSPI_REG_H__
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#if defined ( __CC_ARM )
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#pragma anon_unions
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#endif
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typedef
struct
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{
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__IO uint32_t
CTL
;
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__IO uint32_t
CLKDIV
;
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__IO uint32_t
SSCTL
;
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__IO uint32_t
PDMACTL
;
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__IO uint32_t
FIFOCTL
;
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__IO uint32_t
STATUS
;
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__I uint32_t RESERVE0[2];
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__O uint32_t
TX
;
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__I uint32_t RESERVE1[3];
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__I uint32_t
RX
;
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}
QSPI_T
;
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#define QSPI_CTL_QSPIEN_Pos (0)
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#define QSPI_CTL_QSPIEN_Msk (0x1ul << QSPI_CTL_QSPIEN_Pos)
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#define QSPI_CTL_RXNEG_Pos (1)
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#define QSPI_CTL_RXNEG_Msk (0x1ul << QSPI_CTL_RXNEG_Pos)
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#define QSPI_CTL_TXNEG_Pos (2)
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#define QSPI_CTL_TXNEG_Msk (0x1ul << QSPI_CTL_TXNEG_Pos)
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#define QSPI_CTL_CLKPOL_Pos (3)
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#define QSPI_CTL_CLKPOL_Msk (0x1ul << QSPI_CTL_CLKPOL_Pos)
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#define QSPI_CTL_SUSPITV_Pos (4)
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#define QSPI_CTL_SUSPITV_Msk (0xful << QSPI_CTL_SUSPITV_Pos)
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#define QSPI_CTL_DWIDTH_Pos (8)
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#define QSPI_CTL_DWIDTH_Msk (0x1ful << QSPI_CTL_DWIDTH_Pos)
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#define QSPI_CTL_LSB_Pos (13)
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#define QSPI_CTL_LSB_Msk (0x1ul << QSPI_CTL_LSB_Pos)
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#define QSPI_CTL_HALFDPX_Pos (14)
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#define QSPI_CTL_HALFDPX_Msk (0x1ul << QSPI_CTL_HALFDPX_Pos)
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#define QSPI_CTL_RXONLY_Pos (15)
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#define QSPI_CTL_RXONLY_Msk (0x1ul << QSPI_CTL_RXONLY_Pos)
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#define QSPI_CTL_TWOBIT_Pos (16)
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#define QSPI_CTL_TWOBIT_Msk (0x1ul << QSPI_CTL_TWOBIT_Pos)
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#define QSPI_CTL_UNITIEN_Pos (17)
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#define QSPI_CTL_UNITIEN_Msk (0x1ul << QSPI_CTL_UNITIEN_Pos)
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#define QSPI_CTL_SLAVE_Pos (18)
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#define QSPI_CTL_SLAVE_Msk (0x1ul << QSPI_CTL_SLAVE_Pos)
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#define QSPI_CTL_REORDER_Pos (19)
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#define QSPI_CTL_REORDER_Msk (0x1ul << QSPI_CTL_REORDER_Pos)
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#define QSPI_CTL_DATDIR_Pos (20)
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#define QSPI_CTL_DATDIR_Msk (0x1ul << QSPI_CTL_DATDIR_Pos)
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#define QSPI_CTL_DUALIOEN_Pos (21)
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#define QSPI_CTL_DUALIOEN_Msk (0x1ul << QSPI_CTL_DUALIOEN_Pos)
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#define QSPI_CTL_QUADIOEN_Pos (22)
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#define QSPI_CTL_QUADIOEN_Msk (0x1ul << QSPI_CTL_QUADIOEN_Pos)
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#define QSPI_CLKDIV_DIVIDER_Pos (0)
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#define QSPI_CLKDIV_DIVIDER_Msk (0x1fful << QSPI_CLKDIV_DIVIDER_Pos)
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#define QSPI_SSCTL_SS_Pos (0)
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#define QSPI_SSCTL_SS_Msk (0x1ul << QSPI_SSCTL_SS_Pos)
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#define QSPI_SSCTL_SSACTPOL_Pos (2)
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#define QSPI_SSCTL_SSACTPOL_Msk (0x1ul << QSPI_SSCTL_SSACTPOL_Pos)
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#define QSPI_SSCTL_AUTOSS_Pos (3)
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#define QSPI_SSCTL_AUTOSS_Msk (0x1ul << QSPI_SSCTL_AUTOSS_Pos)
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#define QSPI_SSCTL_SLV3WIRE_Pos (4)
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#define QSPI_SSCTL_SLV3WIRE_Msk (0x1ul << QSPI_SSCTL_SLV3WIRE_Pos)
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#define QSPI_SSCTL_SLVTOIEN_Pos (5)
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#define QSPI_SSCTL_SLVTOIEN_Msk (0x1ul << QSPI_SSCTL_SLVTOIEN_Pos)
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#define QSPI_SSCTL_SLVTORST_Pos (6)
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#define QSPI_SSCTL_SLVTORST_Msk (0x1ul << QSPI_SSCTL_SLVTORST_Pos)
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#define QSPI_SSCTL_SLVBEIEN_Pos (8)
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#define QSPI_SSCTL_SLVBEIEN_Msk (0x1ul << QSPI_SSCTL_SLVBEIEN_Pos)
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#define QSPI_SSCTL_SLVURIEN_Pos (9)
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#define QSPI_SSCTL_SLVURIEN_Msk (0x1ul << QSPI_SSCTL_SLVURIEN_Pos)
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#define QSPI_SSCTL_SSACTIEN_Pos (12)
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#define QSPI_SSCTL_SSACTIEN_Msk (0x1ul << QSPI_SSCTL_SSACTIEN_Pos)
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#define QSPI_SSCTL_SSINAIEN_Pos (13)
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#define QSPI_SSCTL_SSINAIEN_Msk (0x1ul << QSPI_SSCTL_SSINAIEN_Pos)
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#define QSPI_SSCTL_SLVTOCNT_Pos (16)
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#define QSPI_SSCTL_SLVTOCNT_Msk (0xfffful << QSPI_SSCTL_SLVTOCNT_Pos)
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#define QSPI_PDMACTL_TXPDMAEN_Pos (0)
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#define QSPI_PDMACTL_TXPDMAEN_Msk (0x1ul << QSPI_PDMACTL_TXPDMAEN_Pos)
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#define QSPI_PDMACTL_RXPDMAEN_Pos (1)
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#define QSPI_PDMACTL_RXPDMAEN_Msk (0x1ul << QSPI_PDMACTL_RXPDMAEN_Pos)
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#define QSPI_PDMACTL_PDMARST_Pos (2)
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#define QSPI_PDMACTL_PDMARST_Msk (0x1ul << QSPI_PDMACTL_PDMARST_Pos)
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#define QSPI_FIFOCTL_RXRST_Pos (0)
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#define QSPI_FIFOCTL_RXRST_Msk (0x1ul << QSPI_FIFOCTL_RXRST_Pos)
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#define QSPI_FIFOCTL_TXRST_Pos (1)
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#define QSPI_FIFOCTL_TXRST_Msk (0x1ul << QSPI_FIFOCTL_TXRST_Pos)
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#define QSPI_FIFOCTL_RXTHIEN_Pos (2)
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#define QSPI_FIFOCTL_RXTHIEN_Msk (0x1ul << QSPI_FIFOCTL_RXTHIEN_Pos)
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#define QSPI_FIFOCTL_TXTHIEN_Pos (3)
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#define QSPI_FIFOCTL_TXTHIEN_Msk (0x1ul << QSPI_FIFOCTL_TXTHIEN_Pos)
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#define QSPI_FIFOCTL_RXTOIEN_Pos (4)
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#define QSPI_FIFOCTL_RXTOIEN_Msk (0x1ul << QSPI_FIFOCTL_RXTOIEN_Pos)
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#define QSPI_FIFOCTL_RXOVIEN_Pos (5)
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#define QSPI_FIFOCTL_RXOVIEN_Msk (0x1ul << QSPI_FIFOCTL_RXOVIEN_Pos)
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#define QSPI_FIFOCTL_TXUFPOL_Pos (6)
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#define QSPI_FIFOCTL_TXUFPOL_Msk (0x1ul << QSPI_FIFOCTL_TXUFPOL_Pos)
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#define QSPI_FIFOCTL_TXUFIEN_Pos (7)
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#define QSPI_FIFOCTL_TXUFIEN_Msk (0x1ul << QSPI_FIFOCTL_TXUFIEN_Pos)
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#define QSPI_FIFOCTL_RXFBCLR_Pos (8)
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#define QSPI_FIFOCTL_RXFBCLR_Msk (0x1ul << QSPI_FIFOCTL_RXFBCLR_Pos)
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#define QSPI_FIFOCTL_TXFBCLR_Pos (9)
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#define QSPI_FIFOCTL_TXFBCLR_Msk (0x1ul << QSPI_FIFOCTL_TXFBCLR_Pos)
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#define QSPI_FIFOCTL_RXTH_Pos (24)
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#define QSPI_FIFOCTL_RXTH_Msk (0x7ul << QSPI_FIFOCTL_RXTH_Pos)
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#define QSPI_FIFOCTL_TXTH_Pos (28)
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#define QSPI_FIFOCTL_TXTH_Msk (0x7ul << QSPI_FIFOCTL_TXTH_Pos)
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#define QSPI_STATUS_BUSY_Pos (0)
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#define QSPI_STATUS_BUSY_Msk (0x1ul << QSPI_STATUS_BUSY_Pos)
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#define QSPI_STATUS_UNITIF_Pos (1)
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#define QSPI_STATUS_UNITIF_Msk (0x1ul << QSPI_STATUS_UNITIF_Pos)
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#define QSPI_STATUS_SSACTIF_Pos (2)
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#define QSPI_STATUS_SSACTIF_Msk (0x1ul << QSPI_STATUS_SSACTIF_Pos)
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#define QSPI_STATUS_SSINAIF_Pos (3)
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#define QSPI_STATUS_SSINAIF_Msk (0x1ul << QSPI_STATUS_SSINAIF_Pos)
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#define QSPI_STATUS_SSLINE_Pos (4)
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#define QSPI_STATUS_SSLINE_Msk (0x1ul << QSPI_STATUS_SSLINE_Pos)
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#define QSPI_STATUS_SLVTOIF_Pos (5)
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#define QSPI_STATUS_SLVTOIF_Msk (0x1ul << QSPI_STATUS_SLVTOIF_Pos)
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#define QSPI_STATUS_SLVBEIF_Pos (6)
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#define QSPI_STATUS_SLVBEIF_Msk (0x1ul << QSPI_STATUS_SLVBEIF_Pos)
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#define QSPI_STATUS_SLVURIF_Pos (7)
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#define QSPI_STATUS_SLVURIF_Msk (0x1ul << QSPI_STATUS_SLVURIF_Pos)
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#define QSPI_STATUS_RXEMPTY_Pos (8)
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#define QSPI_STATUS_RXEMPTY_Msk (0x1ul << QSPI_STATUS_RXEMPTY_Pos)
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#define QSPI_STATUS_RXFULL_Pos (9)
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#define QSPI_STATUS_RXFULL_Msk (0x1ul << QSPI_STATUS_RXFULL_Pos)
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#define QSPI_STATUS_RXTHIF_Pos (10)
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#define QSPI_STATUS_RXTHIF_Msk (0x1ul << QSPI_STATUS_RXTHIF_Pos)
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#define QSPI_STATUS_RXOVIF_Pos (11)
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#define QSPI_STATUS_RXOVIF_Msk (0x1ul << QSPI_STATUS_RXOVIF_Pos)
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#define QSPI_STATUS_RXTOIF_Pos (12)
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#define QSPI_STATUS_RXTOIF_Msk (0x1ul << QSPI_STATUS_RXTOIF_Pos)
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#define QSPI_STATUS_QSPIENSTS_Pos (15)
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#define QSPI_STATUS_QSPIENSTS_Msk (0x1ul << QSPI_STATUS_QSPIENSTS_Pos)
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#define QSPI_STATUS_TXEMPTY_Pos (16)
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#define QSPI_STATUS_TXEMPTY_Msk (0x1ul << QSPI_STATUS_TXEMPTY_Pos)
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#define QSPI_STATUS_TXFULL_Pos (17)
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#define QSPI_STATUS_TXFULL_Msk (0x1ul << QSPI_STATUS_TXFULL_Pos)
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#define QSPI_STATUS_TXTHIF_Pos (18)
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#define QSPI_STATUS_TXTHIF_Msk (0x1ul << QSPI_STATUS_TXTHIF_Pos)
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#define QSPI_STATUS_TXUFIF_Pos (19)
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#define QSPI_STATUS_TXUFIF_Msk (0x1ul << QSPI_STATUS_TXUFIF_Pos)
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#define QSPI_STATUS_TXRXRST_Pos (23)
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#define QSPI_STATUS_TXRXRST_Msk (0x1ul << QSPI_STATUS_TXRXRST_Pos)
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#define QSPI_STATUS_RXCNT_Pos (24)
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#define QSPI_STATUS_RXCNT_Msk (0xful << QSPI_STATUS_RXCNT_Pos)
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#define QSPI_STATUS_TXCNT_Pos (28)
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#define QSPI_STATUS_TXCNT_Msk (0xful << QSPI_STATUS_TXCNT_Pos)
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#define QSPI_TX_TX_Pos (0)
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#define QSPI_TX_TX_Msk (0xfffffffful << QSPI_TX_TX_Pos)
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#define QSPI_RX_RX_Pos (0)
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#define QSPI_RX_RX_Msk (0xfffffffful << QSPI_RX_RX_Pos)
/* QSPI_CONST */
/* end of QSPI register group */
/* end of REGISTER group */
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#if defined ( __CC_ARM )
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#pragma no_anon_unions
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#endif
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#endif
/* __QSPI_REG_H__ */
QSPI_T
Definition:
qspi_reg.h:27
QSPI_T::STATUS
__IO uint32_t STATUS
Definition:
qspi_reg.h:790
QSPI_T::SSCTL
__IO uint32_t SSCTL
Definition:
qspi_reg.h:787
QSPI_T::FIFOCTL
__IO uint32_t FIFOCTL
Definition:
qspi_reg.h:789
QSPI_T::RX
__I uint32_t RX
Definition:
qspi_reg.h:798
QSPI_T::PDMACTL
__IO uint32_t PDMACTL
Definition:
qspi_reg.h:788
QSPI_T::TX
__O uint32_t TX
Definition:
qspi_reg.h:794
QSPI_T::CTL
__IO uint32_t CTL
Definition:
qspi_reg.h:785
QSPI_T::CLKDIV
__IO uint32_t CLKDIV
Definition:
qspi_reg.h:786
Generated on Fri Jan 12 2024 10:46:52 for M480 BSP by
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